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參數(shù)資料
| 型號： | AKD4395(AKD4395) |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Evaluation board Rev.C for AK4395 |
| 中文描述： | 評價AK4395板Rev.C |
| 文件頁數(shù)： | 5/25頁 |
| 文件大小： | 412K |
| 代理商： | AKD4395(AKD4395) |
ASAHI KASEI
[AKD4395]
<KM063300>
5
2000/7
4. DIP switch set-up
Confirm the set-up of the DIP switch before the operation. “ON” means “H” and “OFF” means “L”.
4-1.System Clock
There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the sampling speed is
set by DFS0/1(Table 1,4). CKS0/1/2 set the frequency of MCLK at each sampling speed (Table 2,5). In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 9), and the internal master clock becomes the
appropriate frequency, it is not necessary to set DFS0/1 and CKS0/1/2. In parallel mode, CKS2 and DFS1 are fixed to “0”.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4395 is in normal operation mode (PD
= “H”). If these clocks are not provided, the AK4395 may draw excess current because the device utilizes dynamic refreshed
logic internally. If the external clocks are not present, the AK4395 should be in the power-down mode (PDN = “L”) or in the
reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4395 is in power-down mode until MCLK and LRCK are
input.
Parallel Mode :
DFS0
(SW3-1)
OFF
ON
Sampling Rate (fs)
Normal Speed Mode
Double Speed Mode
30kHz~54kHz
60kHz~108kHz
Default
Table 1.Sampling Speed (Manual Setting Mode)
Note: DFS1(Register 00H) can be set at only serial mode.
Mode
ACKS
(SW4-3)
OFF
OFF
OFF
OFF
CKS1
(SW4-2)
OFF
OFF
ON
ON
CKS0
(SW4-1)
OFF
ON
OFF
ON
Normal
Double
Quad
0
1
2
3
256fs
256fs
384fs
384fs
512fs
/768fs
128fs
256fs
192fs
384fs
256fs
/384fs
N/A
N/A
N/A
N/A
128fs
/192fs
Default
*
ON
*
*
Table 2. Master Clock (Manual Setting Mode)
Note: When ACKS is ON, Auto Setting Mode is enabled.
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