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參數(shù)資料
| 型號(hào)： | AKD4394 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | EVALUATION BOARD REV.C FOR AK4394 |
| 中文描述： | 評(píng)價(jià)委員會(huì)REV.C的AK4394 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大小： | 398K |
| 代理商： | AKD4394 |
ASAHI KASEI
[AKD4394]
<KM063001>
3
’00/05
<
The evaluation modes and corresponding jumper pins setting
1. Evaluation Modes
Applicable Evaluation Mode
(1) DIR(Optical Link)
(2) Ideal sine wave generated by ROM data
(3) Using AD converted data
(4)All interface signals including master clock are fed externally.
(1) DIR(Optical Link) (default)
PORT2 is used for the evaluation using such as CD test disk. The DIR generates MCLK, BICK and LRCK SDATAfrom
the received data through optical connector(PORT2: TORX176).
Fig.3 Jumper set-up (DIR)
(2) Ideal sine wave generated by ROM data
Digital signal generated by AKD43XX are used. PORT1 is used for the interface with AKD43XX. Master clock is sent
from AKD4394 to AKD43XX then LRCK, BICK and SDATA are sent from AKD43XX to AKD4394.
JP7
SD
JP6
LR
XTL/EXT
DIR
JP5
BI
XTL/EXT
DIR
CLK
JP9
DIR
EXT
XTL
JP8
CKDIV 1
2X
1X
JP4
BCP
INV
THR
JP2
CS8414
VDD
GND
JP1
JP14
CKDIV 2
1/2X
1X
XTL
Fig.4 Jumper set-up (ROM data)
JP7
SD
JP6
LR
XTL/EXT
DIR
JP5
BI
XTL/EXT
DIR
CLK
JP9
DIR
EXT
XTL
JP4
JP8
CKDIV1
2X
1X
BCP
INV
THR
BCP
INV
THR
(others)
(MSB
justified)
JP2
CS8414
VDD
GND
JP1
JP14
CKDIV2
1/2X
1X
XTL
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| AKD4394(AKD4394) | Evaluation board Rev.C for AK4394 |
| AKD4394.(AKD4394) | Evaluation board Rev.C for AK4394 |
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| AKD4395(AKD4395) | Evaluation board Rev.C for AK4395 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| AKD4394(AKD4394) | 制造商:AKM 制造商全稱:AKM 功能描述:Evaluation board Rev.C for AK4394 |
| AKD4394.(AKD4394) | 制造商:AKM 制造商全稱:AKM 功能描述:Evaluation board Rev.C for AK4394 |
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| AKD4395(AKD4395) | 制造商:AKM 制造商全稱:AKM 功能描述:Evaluation board Rev.C for AK4395 |
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