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參數(shù)資料
| 型號： | AKD4386 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
| 中文描述： | 100dB的96kHz的24位二通 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 129K |
| 代理商： | AKD4386 |
ASAHI KASEI
[AK4386]
MS0280-E-00
2003/12
- 9 -
OPERATION OVERVIEW
n
System Clock
The external clocks, which are required to operate the AK4386, are MCLK, BICK and LRCK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK
automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 pins (Table 1).
The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 pin = DFS0 pin
= “H”) (Table 2).
The AK4386 is automatically placed in the power save mode when MCLK stops in the normal operation mode (PDN pin
= “H”), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4386 is powered up. After
exiting reset at power-up etc., the AK4386 is in the power-down mode until MCLK and LRCK are input.
When the states of DIF1-0 pins change in the normal operation mode, the AK4386 should be reset by PDN pin.
Mode
DFS1
DFS0
Normal Speed
L
L
Double Speed
L
H
Half Speed
H
L
Auto
H
H
Table 1. System Clock Example
MCLK Frequency
Sampling Speed Mode
512/768fs
Normal Speed
128/192/256/384fs
Double Speed
1024/1536fs
Half Speed
Table 2. Auto Mode
n
Audio Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 pins as shown in Table 3 can select four
serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of
BICK. Mode 3 can be used for 16bit I
2
S Compatible format by zeroing the unused LSBs at BICK
≥
48fs or BICK = 32fs.
Mode
DIF1
DIF0
0
L
L
16bit, LSB justified
1
L
H
24bit, LSB justified
2
H
L
24bit, MSB justified
3
H
H
16/24bit, I
2
S Compatible
Table 3. Audio Interface Format
fs
MCLK Frequency
256/384/512/768fs
128/192/256/384fs
512/768/1024/1536fs
Table 2
8
～
48kHz
48
～
96kHz
8
～
24kHz
8
～
96kHz
fs
8
～
48kHz
48
～
96kHz
8
～
24kHz
SDTI Format
BICK
≥
32fs
≥
48fs
≥
48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
≥
48fs or 32fs
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PDF描述 |
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| AK4386 | 100DB 96KHZ 24 BIT 2CH |
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相關(guān)代理商/技術(shù)參數(shù) |
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| AKD4386_05 | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz D/A converter for portable audio and home audio systems |
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| AKD4387-SB | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz sampling 24Bit DAC |
| AKD4388 | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit 2ch ツヒ DAC |
| AKD4388A | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit 2ch ΔΣ DAC |
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