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參數(shù)資料
| 型號： | AKD4384 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:3; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:12-3 RoHS Compliant: No |
| 中文描述： | 一零六分貝192kHz的24位2通道數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大小： | 241K |
| 代理商： | AKD4384 |
ASAHI KASEI
[AK4384]
MS0176-E-00
2002/09
- 16 -
n
Mode Control Interface
Some function of the AK4384 can be controlled by pins (parallel control mode) shown in Table 11. The serial control
interface is enabled by the P/S pin = “L”. Internal registers may be written by 3-wire μP interface pins, CSN, CCLK and
CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”,
Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4384 latches the data on the rising
edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “
↑
”. The clock
speed of CCLK is 5MHz (max).
Function
Double sampling mode at 128/192fs
De-emphasis
SMUTE
Zero Detection
16/20/24bit LSB justified format
Table 11. . Function list (O: available, X: not available)
PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4384 should be reset by
PDN= “L”. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.
Parallel mode
X
X
O
O
X
Serial mode
O
O
O
O
O
CDTI
CCLK
CSN
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
C1-C0: Chip Address (Fixed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 8. Control I/F Timing
*The AK4384 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4384 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register
is inhibited.
n
Register Map
Addr
Register Name
D7
D6
D5
00H
Control 1
ACKS
0
0
01H
Control 2
DZFE
DZFM
SLOW
02H
Control 3
0
0
0
03H
Lch ATT
ATT7
ATT6
ATT5
04H
Rch ATT
ATT7
ATT6
ATT5
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values.
All data can be written to the register even if PW or RSTN bit is “0”.
D4
DIF2
DFS1
INVL
ATT4
ATT4
D3
DIF1
DFS0
INVR
ATT3
ATT3
D2
DIF0
DEM1
DZFB
ATT2
ATT2
D1
PW
DEM0
0
ATT1
ATT1
D0
RSTN
SMUTE
0
ATT0
ATT0
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