參數(shù)資料
型號(hào): AKD4381
廠(chǎng)商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 108DB 192KHZ 24-BIT 2CH DAC
中文描述: 108DB 192kHz的24位2聲道數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù): 18/21頁(yè)
文件大?。?/td> 232K
代理商: AKD4381
ASAHI KASEI
[AK4381]
MS0152-E-00
2002/5
- 18 -
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
Addr
Register Name
D7
D6
D5
02H
Control 3
0
0
0
default
0
0
0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
Addr
Register Name
D7
D6
D5
03H
Lch ATT
ATT7
ATT6
ATT5
04H
Rch ATT
ATT7
ATT6
ATT5
default
1
1
1
ATT = 20 log
10
(ATT_DATA / 255) [dB]
00H: Mute
SYSTEM DESIGN
Figure 9 shows the system connection diagram. An evaluation board (AKD4381) is available in order to allow an easy
study on the layout of a surrounding circuit.
D4
0
0
D3
0
0
D2
DZFB
0
D1
0
0
D0
0
0
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
MCLK
1
BICK
2
SDTI
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI
8
DZFL
16
DZFR
15
VDD
14
VSS
13
AOUTL+
12
AOUTL-
11
AOUTR+
10
AOUTR-
9
Master Clock
Micro-
controller
AK4381
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u
+
Lch
LPF
Rch
LPF
Rch Out
Lch Out
MUTE
Analog Ground
Digital Ground
Lch
MUTE
Rch
MUTE
Analog
Supply 5V
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
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AKD4386 ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting
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