參數(shù)資料
型號(hào)： AKD4364(AKD4364)
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Evaluation board Rev.A for AK4364
中文描述： 評(píng)價(jià)AK4364板版本A
文件頁數(shù)： 3/30頁
文件大小： 300K
代理商： AKD4364(AKD4364)
ASAHI KASEI
[AKD4364]
<KM061301>
’00/4
- 3 -
2) Ideal sine wave generated by ROM data
Digital signals generated by AKD43XX are used. PORT3 (ADC/ROM) is used to interface with AK43XX.
Master clock is sent from AKD4364 to AKD43XX and LRCK, BICK, SDTI are supplied from AKD43XX to
AKD4364. In case of using external clock through a BNC connector (J4), select “BNC” on JP14 (CLK) and
short JP15 (XTE).
JP12
DIR_DATA
LRCK
BICK
JP14
CLK
JP6
DIR
ADC
DIR
BNC
XTL
JP7
DIR
ADC
JP13
DIR
VD
GND
JP15
XTE
3) DIR(CS8414)
PORT4 (TORX174) is used for the evaluation using such as test disk. The DIR generates MCKI, BICK,
LRCK, SDTI from the received data through optical connector. In this case, the EXT bit of AK4364 should be
“1” (External clock mode). Select “RCA” or “OPT” on JP16 (RCA/OPT) in case of using RCA connector (J3)
or optical connector (PORT4: TORX174).
JP12
DIR_DATA
LRCK
BICK
JP14
CLK
JP6
DIR
ADC
DIR
BNC
XTL
JP7
DIR
ADC
JP13
DIR
VD
GND
JP15
XTE
n
Clock (MCLK,BICK,LRCK) set up
In case of using evaluation mode 1), JP9,10 and 17 should be set up as follows.
They need no care for other evaluation mode.
MCLK
JP9
(X_MCLK)
x1
JP10
(X_LRCK)
x1/128
BICK
JP17
(X_BICK)
x1/4
x1/2
x1
x1/8
x1/4
x1/2
x1/8
x1/4
x1/2
x1/8
x1/4
x1/2
128fs
32fs
64fs
128fs
32fs
64fs
128fs
32fs
64fs
128fs
32fs
64fs
128fs
256fs
x1
x1/256
default
512fs
x2
x1/256
1024fs
x4
x1/256
Table 1. Clock set up
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