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參數(shù)資料
| 型號： | AKD4358 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:22; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:12-35 RoHS Compliant: No |
| 中文描述： | 192千赫24位8路DAC，具有DSD輸入 |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 457K |
| 代理商： | AKD4358 |
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ASAHI KASEI
[AK4358]
MS0203-E-00
2003/02
- 14 -
LRCK
fs
88.2kHz
96.0kHz
MCLK
BICK
64fs
5.6448MHz
6.1440MHz
128fs
192fs
256fs
384fs
11.2896MHz 16.9344MHz
12.2880MHz 18.4320MHz
22.5792MHz
24.5760MHz
33.8688MHz
36.8640MHz
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
MCLK
fs
128fs
176.4kHz
22.5792MHz
33.8688MHz
192.0kHz
24.5760MHz
36.8640MHz
BICK
64fs
192fs
11.2896MHz
12.2880MHz
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
Sampling Speed
Normal
Double
Quad
Table 6. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
256fs
-
-
-
22.5792
24.5760
-
-
128fs
-
-
-
-
-
22.5792
24.5760
192fs
-
-
-
-
-
33.8688
36.8640
384fs
-
-
-
33.8688
36.8640
-
-
512fs
16.3840
22.5792
24.5760
-
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
Sampling Speed
Normal
Double
Quad
Table 7. System Clock Example (Auto Setting Mode)
ACKSN pin
ACKS bit
0
0
0
1
1
0
1
1
Table 8. Relationship between ACKSN pin and ACKS bit
Clock Mode
Manual Setting Mode
Auto Setting Mode
Manual Setting Mode
Manual Setting Mode
(Default)
2) DSD Mode
The external clocks, which are required to operate the AK4358, are MCLK and DCLK. The master clock (MCLK) should
be synchronized with DSD clock (DCLK) but the phase is not critical. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4358 is in the normal operation mode
(PDN= ”H”). If these clocks are not provided, the AK4358 may draw excess current because the device utilizes dynamic
refreshed logic internally. The AK4358 should be reset by PDN= ”L” after threse clocks are provided. If the external
clocks are not present, the AK4358 should be in the power-down mode (PDN= ”L”). After exiting reset(PDN = “
↑
”) at
power-up etc., the AK4358 is in the power-down mode until MCLK is input. PCM interface signals (BICK, LRCK,
SDTI1-4) are fixed to “H” or “L”.
相關PDF資料 |
PDF描述 |
|---|---|
| AK4358VQ | 192 KHZ 24 BIT 8 CH DAC WITH DSD INPUT |
| AK4359 | 192 KHZ 24 BIT 8CH DAC |
| AKD4359 | Circular Connector; No. of Contacts:22; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:12-35 RoHS Compliant: No |
| AK4359VF | 192 KHZ 24 BIT 8CH DAC |
| AK4360 | Low Power 2ch ΔΣ DAC with HP-AMP(帶耳機放大器的20位低電壓低功耗立體聲D/A轉(zhuǎn)換器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AKD4358-B | 制造商:AKM 制造商全稱:AKM 功能描述:digital audio interface that can interface with digital audio systems via opt-connector or RCA connector |
| AKD4359 | 制造商:AKM 制造商全稱:AKM 功能描述:106dB 192kHz 24-Bit 8ch DAC |
| AKD4359A | 制造商:AKM 制造商全稱:AKM 功能描述:106dB 192kHz 24-Bit 8ch DAC |
| AKD4359-SC | 制造商:AKM 制造商全稱:AKM 功能描述:the 24bit 8ch D/A converter. |
| AKD4363 | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz 24Bit DAC with PLL |
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