參數(shù)資料
型號(hào): AKD4356
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: EVALUATION BOARD REV.B FOR AK4356
中文描述: 評(píng)價(jià)委員會(huì)REV.B的AK4356
文件頁數(shù): 3/27頁
文件大?。?/td> 297K
代理商: AKD4356
ASAHI KASEI
[AKD4356]
<KM060602>
’99/11
- 3 -
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Operation sequence
1) Set up the power supply lines.
[AVDD]
(orange)
[DVDD]
(orange)
[VD]
(red)
[VP+]
(green) = +12V
+15V
[VP-]
(blue)
[AGND]
(black) = 0V
[DGND]
(black) = 0V
= 4.5
5.25V
= 4.5
5.25V
= 3.4
5.0V
= -12V
-12V
Each supply line should be distributed from the power supply unit.
2) Set-up the evaluation modes, jumper pins and DIP switches
(See the followings.)
3) Power on.
The AK4356 should be reset once bringing SW1(-PD) “L” upon power-up.
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Evaluation mode
Applicable evaluation modes
1) DIR (Optical Link and RCA) (default)
2) Using ROM data (AK43XX)
3) Using AKM’s evaluation board for ADC
4) Feeding all signals from external
1) DIR (Optical Link and RCA) <default>
PORT4(TORX174) or J1(RCA) is used. All clock are supplied from CS8414(DIR). DIR generates MCLK,
BICK, LRCK and SDATA from the received data through optical connector (TORX174) or RCA connector.
Used for the evaluation using CD test disk. Nothing should be connected to PORT2,3. In case of using optical
connector (TORX174), select “OPT” on JP17(RCA/OPT). In case of using RCA connector, select “RCA”.
JP15
XTI
JP14
DIR
JP4
LRCK
DIR
ADC
JP7
BICK
JP16
XTE
JP13
SDATA
DIR
ADC
D
B
X
GND
VD
2) Ideal sine wave generated by ROM data
Connect the AKD43XX with PORT3(AD/ROM). AKD4356 sends MCLK to AKD43XX, and receives LRCK,
BICK and SDATA. In case of using external master clock through a BNC connector, select “BNC” on JP15(XTI)
and short JP16(XTE).
JP15
XTI
JP14
DIR
JP4
LRCK
DIR
ADC
JP7
BICK
JP16
XTE
JP13
SDATA
DIR
ADC
D
B
X
GND
VD
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