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參數(shù)資料
| 型號： | AK9844F |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Aluminum Snap-In Capacitor; Capacitance: 470uF; Voltage: 160V; Case Size: 25x25 mm; Packaging: Bulk |
| 中文描述： | 4Kbit EEPROM，帶有4通道8位D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 156K |
| 代理商： | AK9844F |
ASAHI KASEI
[AK9844]
DAD02E-00
1999/05
- 8 -
Instruction Set
The AK9844 has 6 instructions such as READ, WRITE, WREN, WRDS, PDEN, PDDS. Each instruction
consists of Op-code, address and data. The instruction set is showed on table.6.
When the instructions are executed consecutively, the CS pin should be brought to high level for a minimum of
1us(tCS) between consecutive instruction cycle.
Instruction
READ
WRITE
WREN
WRDS
PDEN
PDDS
Op-code
1 0 1 0 1 0 0
1 0 1 0 0 1 0
1 0 1 0 0 0 1
1 0 1 0 0 0 0
1 0 1 0 1 1 0
1 0 1 0 0 1 1
Address
Data
D15
～
D0
D15
～
D0
～
～
～
～
Comments
A8
A8
1
0
0
0
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
: Don't Care
Table.6 Instruction set
Read register
Write register
Write enable
Write Disable
Power down enable
Power down desable
WRITE
The WRITE instruction is followed by 16 bits of data to be written into the specified address. After the 32nd
rising edge of SK to read DO in, the AK9844 will be put into the automatic write time-out period. During the
automatic write time-out period (Busy status), the CS pin need not be high level.
The DO pin indicates the Ready/Busy status of the EEPROM in AK9844. After the 32nd rising edge of SK to
read DO in, the AK9844 will be put into the automatic write time-out period.
When the automatic write time-out period start, the DO pin outputs the Ready/Busy status.
When the DO pin outputs low level, the AK9844 is in the automatic write time-out and the next instruction can
not be accepted. When the DO pin outputs high level, the automatic write time-out period has ended and the
AK9844 is ready for a next instruction.
When the CS pin is changed to high level after confirmation of Ready/Busy signal on the DO pin, the DO pin
becomes "Hi-Z". The Ready/Busy signal can be confirmed until the initial 1 bit of the next instruction inputs
from the execution of the WRITE instruction.
WRITE instruction
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