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參數(shù)資料
| 型號(hào)： | AK5394A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | RES, 10K 5% 0.1W, 0603 |
| 中文描述： | 超高性能192kHz的24位ADC |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 174K |
| 代理商： | AK5394A |
ASAHI KASEI
[AK5394A]
MS0137-E-01
2002/07
- 13 -
OPERATION
OVERVIEW
System Clock Input
The external clocks that are required to operate the AK5394A are MCLK, LRCK(fs) and SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. Table 1 and 2 show the relationship between the sampling rate and
the frequencies of MCLK and SCLK.
As the AK5394A includes the phase detect circuit for LRCK, the AK5394A is reset automatically when the
synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
All external clocks must be present unless RSTN pin = “L”, otherwise excessive current may result from abnormal
operation of internal dynamic logic.
Sampling Speed
Normal
L
L
～
54kHz
～
128fs
128fs
256fs
Double
H
L
～
108kHz
～
64fs
64fs
128fs
Quad
L
H
～
216kHz
～
64fs
64fs
64fs
DFS0
DFS1
LRCK (fs)
SCLK (Slave Mode)
SCLK (Master Mode)
MCLK
Table 1. System Clocks
LRCK (fs)
32kHz
44.1kHz
48kHz
96kHz
192kHz
MCLK
8.1920MHz
11.2896MHz
12.2880MHz
12.2880MHz
12.2880MHz
SCLK
～
4.0960MHz
～
5.6448MHz
～
6.1440MHz
～
6.1440MHz
～
12.288MHz
Table 2. Examples of System Clock Frequency
Serial
Data
Interface
The AK5394A supports four serial data formats that can be selected via SMODE1 and SMODE2 pins (Table 3). The data
format is MSB-first, 2’s complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE2
L
L
H
H
SMODE1
L
H
L
H
Table 3. Serial I/F Formats
Mode
LRCK
Slave Mode
Master Mode
I
2
S Slave Mode
I
2
S Master Mode
Lch = H, Rch = L
Lch = H, Rch = L
Lch = L, Rch = H
Lch = L, Rch = H
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