- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385095 > AK5385BVF (Asahi Kasei Microsystems Co.,Ltd) 24Bit 192kHz ツヒ ADC PDF資料下載
參數(shù)資料
| 型號： | AK5385BVF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 24Bit 192kHz ツヒ ADC |
| 中文描述： | ADC的24位192kHz的ツヒ |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 195K |
| 代理商： | AK5385BVF |
ASAHI KASEI
[AK5385B]
MS0406-E-00
2005/08
- 14 -
OPERATION OVERVIEW
System Clock
MCLK (256fs/384fs/512fs), BICK (48fs
～
) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling
frequency and the system clock frequency. MCLK frequency is selected by CKS1-0 pins as shown in Table 2 and LRCK
frequency is selected by DFS1-0 pins as shown in Table 3.
As the AK5385B includes the phase detect circuit for LRCK, the AK5385B is reset automatically when the
synchronization is out of phase by changing the clock frequencies.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5385B may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5385B in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
MCLK
fs
128fs
N/A
N/A
N/A
N/A
256fs
8.192MHz
11.2896MHz
12.288MHz
24.576MHz
N/A
384fs
512fs
32kHz
44.1kHz
48kHz
96kHz
192kHz
12.288MHz
16.9344MHz
18.432MHz
N/A
N/A
16.384MHz
22.5792MHz
24.576MHz
N/A
N/A
24.576MHz
Table 1. System Clock Example
CKS1 pin
L
L
H
H
CKS0 pin
L
H
L
H
Table 2. MCLK Frequency
MCLK Frequency
256fs
128fs
512fs
384fs
DFS1 pin
L
L
H
H
DFS0 pin
L
H
L
H
Table 3. Sampling Speed
LRCK Frequency
8kHz
≤
fs
≤
54kHz
54kHz
<
fs
≤
108kHz
108kHz
<
fs
≤
216kHz
N/A
When changing MCLK frequency in master/slave mode, the AK5385B should reset by PDN pin = “L”. (ex.
12.288MHz(@fs=48kHz) to 24.576MHz(@fs=96kHz) at CKS1 pin = CKS0 pin = “L”.
If the CKS1-0 and DFS1-0 pins are changed with same MCLK frequency in master/slave mode (ex. MCLK is fixed to
24.576MHz and fs is changed from 48kHz (CKS1 pin = “L”, CKS0 pin = “L”) to 96kHz (CKS1 pin = “L”, CKS0 pin =
“H”)), no reset by PDN pin = “L” is required.
相關PDF資料 |
PDF描述 |
|---|---|
| AK5385BVS | 24Bit 192kHz ツヒ ADC |
| AK5386 | Single-ended 24-Bit 192kHz ツヒ ADC |
| AK5386VT | Single-ended 24-Bit 192kHz ツヒ ADC |
| AK5388 | 120dB 24-bit 192kHz 4-Channel ADC |
| AK5392 | Enhanced Dual Bit 24Bit ADC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK5385BVFP-E2 | 功能描述:IC ADC AUDIO STER 24BIT 28VSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Data Converter Basics 標準包裝:1 系列:- 類型:電機控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應商設備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| AK5385BVS | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 192kHz ΔΣ ADC |
| AK5385BVSP-E2 | 功能描述:IC ADC AUDIO STER 24BIT 28VSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Data Converter Basics 標準包裝:1 系列:- 類型:電機控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應商設備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| AK5386 | 制造商:AKM 制造商全稱:AKM 功能描述:Single-ended 24-Bit 192kHz ツヒ ADC |
| AK5386VT | 制造商:AKM 制造商全稱:AKM 功能描述:Single-ended 24-Bit 192kHz ツヒ ADC |
發(fā)布緊急采購，3分鐘左右您將得到回復。