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參數(shù)資料
| 型號(hào)： | AK5384 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 107 DB 24 BIT 96KHZ 4 CHANNEL ADC |
| 中文描述： | 107數(shù)據(jù)庫24位96kHz 4通道ADC |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 238K |
| 代理商： | AK5384 |
ASAHI KASEI
[AK5384]
MS0225-E-00
2003/05
- 15 -
n
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz(@fs=48kHz)
and scales with sampling rate (fs).
n
Overflow Detection
The AK5384 has overflow detect function for analog input. OVF pin goes to “H” if one of 4-channels overflows (more
than
0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC
(GD=27.6/fs=575μs@fs=48kHz). OVF is “L” for 516/fs (=10.75ms@fs=48kHz) after PDN pin = “
↑
”, and then overflow
detection is enabled.
n
Power down
The AK5384 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM are AVSS level. An analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO1/2 becomes available after
516 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2’s
complement “0”. The ADC outputs settle in the data corresponding to the input signals after the end of initialization
(Settling approximately takes the group delay time).
Normal Operation
Internal
State
PDN
Power-down
Initialize
Normal Operation
516/fs(10.75ms@fs=48kHz)
Idle Noise
GD
GD
“0”data
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,BICK
(1)
(2)
(3)
“0”data
Idle Noise
Notes:
(1) Digital output corresponding to analog input has the group delay (GD).
(2) ADC output is “0” data at the power-down state.
(3) When the external clocks (MCLK, BICK, LRCK) are stopped, the AK5384 should be in the power-down state.
Figure 7. Power-down/up sequence example
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System Reset
The AK5384 should be reset once by bringing PDN pin “L” after power-up. The internal timing starts clocking by the
rising edge (falling edge at I
2
S mode) of LRCK upon exiting from reset.
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