參數(shù)資料
型號(hào): AK5383VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Enhanced Dual bit 96 kHz 24-bit ADC
中文描述: 增強(qiáng)雙位96 kHz的24位ADC
文件頁數(shù): 4/20頁
文件大小: 123K
代理商: AK5383VF
ASAHI KASEI
[AK5383]
M0049-E-03
2000/4
- 4 -
14
SCLK
I/O
Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA. In I
2
S mode, FSYNC is
Don’t care.
Master mode:
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
Master Clock Input Pin
256fs at DFS="L", 128fs at DFS="H".
Double Speed Sampling Mode Pin
"L": Normal Speed
"H": Double Speed
High Pass Filter Enable Pin
"L": Disable
"H": Enable
Test Pin ( pull-down pin)
Should be connected to GND.
Substrate Ground Pin, 0V
Analog Ground Pin, 0V
Analog Supply Pin, 5V
Rch Analog negative input Pin
Rch Analog positive input Pin
Rch Common Voltage Pin, 2.75V
Rch Reference Ground Pin, 0V
Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10μF electrolytic capacitor and a 0.1μF
ceramic capacitor
15
SDATA
O
16
FSYNC
I/O
17
MCLK
I
18
DFS
I
19
HPFE
I
20
TEST
I
21
22
23
24
25
26
27
28
BGND
AGND
VA
AINR-
AINR+
VCOMR
GNDR
VREFR
-
-
-
I
I
O
-
O
Note: All digital inputs should not be left floating.
相關(guān)PDF資料
PDF描述
AK5383VS Enhanced Dual bit 96 kHz 24-bit ADC
AK5385B 24Bit 192kHz ツヒ ADC
AK5385BVF 24Bit 192kHz ツヒ ADC
AK5385BVS 24Bit 192kHz ツヒ ADC
AK5386 Single-ended 24-Bit 192kHz ツヒ ADC
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