參數(shù)資料
型號(hào): AK5366VQ
廠(chǎng)商: Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi): 圓形連接器
英文描述: Circular Connector; No. of Contacts:6; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-6 RoHS Compliant: No
中文描述: 24位48KHz的ADC,帶選擇器/美國(guó)PGA / ALC的
文件頁(yè)數(shù): 16/43頁(yè)
文件大?。?/td> 338K
代理商: AK5366VQ
ASAHI KASEI
[AK5366
]
MS0309-E-00
2004/05
- 16 -
OPERATION OVERVIEW
System Clock
MCLK (256fs/384fs/512fs), BICK (48fs
) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. MCLK frequency is automatically detected in slave mode.
Table 1 shows the relationship of typical sampling frequency and the system clock frequency. Setting of CKS 1-0 bit is
ignored.
MCLK (256fs/384fs/512fs) is required in master mode. MCLK frequency is selected by CKS1-0 bits as shown in Table 2.
In master mode, after setting CKS1-0 bits, there is a possibility the frequency and duty of LRCK and BICK outputs
become an abnormal state.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L” and PWN bit = “1”. If these clocks
are not provided, the AK5366 may draw excess current due to its use of internal dynamically refreshed logic. If the
external clocks are not present, place the AK5366 in power-down mode (PDN pin = “L” or PWN bit = “0”). In master
mode, the master clock (MCLK) must be provided unless PDN pin = “L”.
MCLK
384fs
12.288MHz
16.9344MHz
18.432MHz
fs
256fs
8.192MHz
11.2896MHz
12.288MHz
Table 1. System clock example (Slave mode)
512fs
32kHz
44.1kHz
48kHz
16.384MHz
22.5792MHz
24.576MHz
CKS1
0
0
1
1
Table 2. Master clock frequency select (Master mode)
CKS0
0
1
0
1
MCLK
256fs
512fs
384fs
N/A
Default
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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