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參數(shù)資料
| 型號： | AK5359 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 24-Bit 192kHz ツヒ ADC |
| 中文描述： | 24位192kHz的ツヒ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 145K |
| 代理商： | AK5359 |
ASAHI KASEI
[AK5359]
MS0428-E-00
2005/09
- 7 -
DC CHARACTERISTICS
(Ta=Tmin
～
Tmax ; VA=4.5
～
5.5V; VD=3.0
～
5.5V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=
1mA)
Low-Level Output Voltage (Iout=1mA)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
min
70%VD
-
VD
0.5
-
-
typ
-
-
-
-
-
max
-
30%VD
-
0.5
±
10
Units
V
V
V
V
μ
A
SWITCHING CHARACTERISTICS
(Ta=Tmin
～
Tmax ; VA=4.5
～
5.5V; VD=3.0
～
5.5V; C
L
=20pF)
Parameter
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
LRCK Frequency
Duty Cycle
Master mode
Audio Interface Timing
Slave mode
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “
↑
” (Note 10)
SCLK “
↑
” to LRCK Edge (Note 10)
LRCK to SDTO (MSB) (Except I
2
S mode)
SCLK “
↓
” to SDTO
Master mode
SCLK Frequency
SCLK Duty
SCLK “
↓
” to LRCK
SCLK “
↓
” to SDTO
Reset Timing
PDN Pulse Width (Note 11)
PDN “
↑
” to SDTO valid at Slave Mode (Note 12)
PDN “
↑
” to SDTO valid at Master Mode (Note 12)
Note 10. SCLK rising edge must not occur at the same time as LRCK edge.
Note 11. The AK5359 can be reset by bringing the PDN pin = “L”.
Note 12. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Symbol
min
2.048
0.4/fCLK
0.4/fCLK
8
45
72
33
33
20
20
20
20
150
typ
50
64fs
50
max
41.472
216
55
25
25
20
20
Units
fCLK
tCLKL
tCLKH
fs
tSCK
tSCKL
tSCKH
tLRSH
tSHLR
tLRS
tSSD
fSCK
dSCK
tMSLR
tSSD
tPD
tPDV
tPDV
MHz
ns
ns
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
Slave mode
4132
4129
ns
1/fs
1/fs
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