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參數(shù)資料
| 型號(hào)： | AK5358 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 26/PG/OP/FLG/THD INS |
| 中文描述： | 96kHz的24位ADC的ツヒ |
| 文件頁數(shù)： | 11/17頁 |
| 文件大小： | 136K |
| 代理商： | AK5358 |
ASAHI KASEI
[AK5358]
MS0438-E-00
2005/11
- 11 -
OPERATION OVERVIEW
System Clock
MCLK, SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with
MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system
clock frequency. MCLK frequency, SCLK frequency and master/slave are selected by CKS2-0 pins as shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5358 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5358 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
MCLK
fs
256fs
8.192MHz
11.2896MHz
12.288MHz
24.576MHz
384fs
512fs
768fs
32kHz
44.1kHz
48kHz
96kHz
12.288MHz
16.9344MHz
18.432MHz
36.864MHz
16.384MHz
22.5792MHz
24.576MHz
N/A
24.576MHz
33.8688MHz
36.864MHz
N/A
Table 1. System Clock Example
Mode
CKS2
CKS1
CKS0
Input Level
Master/Slave
MCLK
SCLK
0
L
L
L
CMOS
Slave
256/384fs (8k
≤
fs
≤
96k)
512/768fs (8k
≤
fs
≤
48k)
Reserved
256fs (8k
≤
fs
≤
96k)
512fs (8k
≤
fs
≤
48k)
Reserved
Reserved
384fs (8k
≤
fs
≤
96k)
768fs (8k
≤
fs
≤
48k)
≥
48fs or 32fs
(Note 13)
1
2
3
4
5
6
7
L
L
L
H
H
H
H
L
H
H
L
L
H
H
H
L
H
L
H
L
H
CMOS
CMOS
CMOS
CMOS
Table 2. Operation Mode Select
Master
Master
Master
Master
64fs
64fs
64fs
64fs
Note 13. SDTO outputs 16bit data at SCLK=32fs.
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