- 您現(xiàn)在的位置：買賣IC網 > PDF目錄385098 > AK5356VN (Asahi Kasei Microsystems Co.,Ltd) Circular Connector; No. of Contacts:42; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-42 RoHS Compliant: No PDF資料下載
參數資料
| 型號： | AK5356VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:42; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-42 RoHS Compliant: No |
| 中文描述： | 低功耗20位ADC，具有麥克風放大器 |
| 文件頁數： | 12/22頁 |
| 文件大?。?/td> | 156K |
| 代理商： | AK5356VN |
ASAHI KASEI
[AK5356]
MS0171-E-00
2002/08
- 12 -
OPERATION OVERVIEW
n
System Clock
The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs, 40fs
～
). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The Frequency of MCLK can be
input at 256fs or 384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically. *fs is sampling
frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these
clocks are not provided, the AK5356 may draw excess current and will not operate properly because it utilizes these clocks
for internal dynamic refresh of registers. If the external clocks are not present, the AK5356 should be placed in
power-down mode.
n
Audio Data I/F Format
The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes,
MSB-first and 2’s compliment. The data format is set using the DIF bit. SDTO is latched by a falling edge of BCLK.
No.
DIF bit
SDTO (ADC)
16bit MSB justified
Lch: “H”, Rch: “L”
0
0
20bit MSB justified
Lch: “H”, Rch: “L”
16bit I
2
S compatible
Lch: “L”, Rch: “H”
1
1
20bit I
2
S compatible
Lch: “L”, Rch: “H”
Table 1. Audio Data Format
LRCK
LRCK
BCLK
= 32fs
≥
40fs
= 32fs
≥
40fs
Default
BCLK(I:64fs)
SDTO(o)
0
1
2
12
13
14
20
21
31
0
1
2
12
13
14
20
21
31
0
19
1
18
0
19 18
8
7
6
0
19
19:MSB, 0:LSB
Lch Data
Rch Data
8
7
6
BCLK(i:32fs)
SDTO (o)
0
1
2
12
10
11
13
3
0
1
2
18
8
18
11 10
17
9
14
17
3
3
7
5
6
4
19
19
15
8
10
9
7
5
6
4
19
11
9
11
9
10
12
15
0
13
14
1
19
19
Figure 7. Audio Data Timing (No.0)
相關PDF資料 |
PDF描述 |
|---|---|
| AKD5383 | EVALUATION BOARD REV.B FOR AK5383VF |
| AKD5384 | 107 DB 24 BIT 96KHZ 4 CHANNEL ADC |
| AK5384 | 107 DB 24 BIT 96KHZ 4 CHANNEL ADC |
| AK5384VF | 107 DB 24 BIT 96KHZ 4 CHANNEL ADC |
| AKD5392 | EVALUATION BOARD REV.B FOR AK5392 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AK5357 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:24 BIT 96 KHZ ADC |
| AK5357_09 | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz ΔΣ ADC |
| AK5357ET | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz ツヒ ADC |
| AK5357ETP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:24BIT 96K 102DB ADC, -20 C TO |
| AK5357KT | 制造商:AKM 制造商全稱:AKM 功能描述:24Bit 96kHz ΔΣ ADC |
發(fā)布緊急采購，3分鐘左右您將得到回復。