參數(shù)資料
型號(hào): AK5355VT
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: LOW POWER 16BIT ADC
中文描述: 低功耗16位ADC
文件頁(yè)數(shù): 8/14頁(yè)
文件大?。?/td> 120K
代理商: AK5355VT
ASAHI KASEI
[AK5355]
MS0113-E-00
2001/08
- 8 -
OPERATION OVERVIEW
System Clock
The clocks required to operate are MCLK (256fs/384fs/512fs), LRCK (fs) and BCLK (32fs
). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be
input as 256fs, 384fs or 512fs. When the 384fs or 512fs is input, the internal master clock is divided into 2/3 or 1/2
automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these
clocks are not provided, the AK5355 may draw excess current and will not operate properly because it utilizes these clocks
for internal dynamic refresh of registers. If the external clocks are not present, the AK5355 should be placed in power-
down mode.
Audio Data I/F Format
The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes, MSB-
first and 2’s compliment. The data format is set using the DIF pin.
No.
0
1
DIF pin
L
H
SDTO (ADC)
16bit MSB justified
I
2
S Compatible
LRCK
BCLK
32fs
32fs
Figure
Figure 4
Figure 5
Lch: “H”, Rch: “L”
Lch: “L”, Rch: “H”
Table 1. Audio Data Format
LRCK
BCLK(32fs)
SDTO(o)
0
1
2
8
9
10
12
13
15
0
1
2
8
9
10
12
13
15
0
15
1
14
4
8
7
6
0
3
2
11
14
1
5
15 14
4
8
7
6
0
3
2
1
5
14
11
15
13
BCLK(64fs)
SDTO(o)
0
1
2
3
14
15
17
18
31
0
1
2
14
15
17
18
31
0
15
1
14
0
15 14
1
2
1
15
15:MSB, 0:LSB
Lch Data
Rch Data
2
1
13
16
0
16
3
13
3
13
13
3
Figure 4. Audio Data Timing (No.0)
LRCK
BCLK(32fs)
SDTO(o)
0
1
2
4
9
10
12
13
15
0
1
2
4
9
10
12
13
15
0
0
1
15
5
13
7
7
1
4
3
11
14
2
6
0
15
5
13
7
7
1
4
3
2
6
14
11
0
13
BCLK(64fs)
SDTO(o)
0
1
2
3
14
15
17
18
31
0
1
2
4
14
15
17
18
31
0
1
15
0
15
13
2
1
15:MSB, 0:LSB
Lch Data
Figure 5. Audio Data Timing (No. 1)
Rch Data
2
1
14
16
0
16
3
14
14
3
2
14
3
4
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