
ASAHI KASEI
[AK4631]
MS0317-J-01
2004/11
- 13 -
Parameter
PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 6, Figure 7)
FCK: Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK: Period
Pulse Width Low
Pulse Width High
PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 6, Figure 7)
FCK: Frequency
DSP Mode: Pulse width High
Except DSP Mode: Duty Cycle
BICK: Period (PLL3-0 = “0001”)
(PLL3-0 = “0010”)
(PLL3-0 = “0011”)
Pulse Width Low
Pulse Width High
PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 8)
MCKI Input: Frequency
Pulse Width Low
Pulse Width High
MCKO Output:
Frequency
Duty Cycle except fs=29.4kHz, 32kHz
fs=29.4kHz, 32kHz (Note 23)
FCK: Frequency
DSP Mode: Pulse width High
Except DSP Mode: Duty Cycle
BICK: Period
Pulse Width Low
Pulse Width High
Audio Interface Timing
DSP Mode: (Figure 9, Figure 10)
FCK “
↑
” to BICK “
↑
” (Note 24)
FCK “
↑
” to BICK “
↓
” (Note 25)
BICK “
↑
” to FCK “
↑
” (Note 24)
BICK “
↓
” to FCK “
↑
” (Note 25)
BICK “
↑
” to SDTO (BCKP = “0”)
BICK “
↓
” to SDTO (BCKP = “1”)
SDTI Hold Time
SDTI Setup Time
Except DSP Mode: (Figure 12)
FCK Edge to BICK “
↑
” (Note 26)
BICK “
↑
” to FCK Edge (Note 26)
FCK to SDTO (MSB) (Except I
2
S mode)
BICK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Symbol
min
typ
max
Units
fFCK
tFCKH
duty
tBCK
tBCKL
tBCKH
7.35
tBCK-60
45
1/64fFCK
240
240
8
26
1/fFCK-tBFCK
55
1/16fFCK
kHz
ns
%
ns
ns
ns
fFCK
tFCKH
duty
tBCK
tBCK
tBCK
tBCKL
tBCKH
7.35
tBCK-60
45
0.4 x tBCK
0.4 x tBCK
8
48
1/fFCK-tBFCK
55
kHz
ns
%
ns
ns
ns
ns
ns
1/16fFCK
1/32fFCK
1/64fFCK
fCLK
fCLKL
fCLKH
fMCK
dMCK
dMCK
fFCK
tFCKH
duty
tBCK
tBCKL
tBCKH
tFCKB
tFCKB
tBFCK
tBFCK
tBSD
tBSD
tSDH
tSDS
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
11.2896
0.4/fCLK
0.4/fCLK
40
8
tBCK-60
45
1/64fFCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
50
50
50
50
50
50
27.0
60
48
MHz
ns
ns
256 x fFCK
50
33
kHz
%
%
kHz
ns
%
ns
ns
ns
1/fFCK-tBFCK
55
1/16fFCK
80
80
80
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns