參數(shù)資料
型號： AK4628
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： HIGH PERFORMANCE MULTI CHANNEL AUDIO CODEC
中文描述： 高性能多通道音頻解碼器
文件頁數(shù)： 18/41頁
文件大小： 546K
代理商： AK4628
ASAHI KASEI
[AK4628]
MS0211-E-02
2004/03
- 18 -
Audio Serial Interface Format
When TDM= “L”, four modes can be selected by the DIF1-0 as shown in Table 8. In all modes the serial data is
MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are
latched on the rising edge of BICK.
Figures 1
～
4 shows the timing at SDOS = “L”. In this case, the SDTO outputs the ADC output data. When SDOS = “H”,
the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2, 3, 6, 7, 10, 11 in SDTI input
formats can be used for 16-20bit data by zeroing the unused LSBs.
Mode
TDM 1
TDM0
DIF1
DIF0
SDTO
LRCK
BICK
SDTI1-4,
DAUX
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I
2
S
I/O
I/O
0
0
0
0
0
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I
2
S
H/L
I
≥
48fs
I
1
0
0
0
1
H/L
I
≥
48fs
I
2
0
0
1
0
H/L
I
≥
48fs
I
Default
3
0
0
1
1
L/H
I
≥
48fs
I
Table 8. Audio data formats (Normal mode)
The audio serial interface format becomes the TDM mode if TDM0 pin is set to “H”. In the TDM256 mode, the serial data
of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should be fixed
to 256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by the DIF1-0 as shown
in Table 9. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge
of BICK and the SDTI1 are latched on the rising edge of BICK. SDOS and LOOP1-0 should be set to “0” at the TDM
mode. TDM128 Mode can be set by TDM1 as show in Table10. In Double Speed Mode, the serial data of DAC (four
channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other four data (L3, R3, L4, R4) are input to the SDTI2. TDM0 pin
and TDM0 register should be set to “H” if TDM256 Mode is selected. TDM0 pin and TDM0 register, TDM1 register
should be set to “H” if Double Speed Mode is selected in TDM128 Mode.
Mode
TDM 1
TDM0
DIF1
DIF0
SDTO
LRCK
BICK
SDTI1
I/O
I/O
4
0
1
0
0
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I
2
S
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I
2
S
↑
I
256fs
I
5
0
1
0
1
↑
I
256fs
I
6
0
1
1
0
↑
I
256fs
I
7
0
1
1
1
↓
I
256fs
I
Table 9. Audio data formats (TDM256 mode)
DIF1
DIF0
SDTO
LRCK
BICK
Mode
TDM 1
TDM0
SDTI1,
SDTI2
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I
2
S
I/O
I/O
8
1
1
0
0
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I
2
S
↑
I
128fs
I
9
1
1
0
1
↑
I
128fs
I
10
1
1
1
0
↑
I
128fs
I
11
1
1
1
1
↓
I
128fs
I
Table 10. Audio data formats (TDM128 mode)
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