- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385093 > AK4620B (Asahi Kasei Microsystems Co.,Ltd) 24-Bit 192kHz Audio CODEC with IPGA PDF資料下載
參數(shù)資料
| 型號： | AK4620B |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 24-Bit 192kHz Audio CODEC with IPGA |
| 中文描述： | 24位192kHz的音頻編解碼器與單親遺傳算法 |
| 文件頁數(shù)： | 26/42頁 |
| 文件大?。?/td> | 410K |
| 代理商： | AK4620B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
ASAHI KASEI
[AK4620B]
MS0401-E-00
2005/07
- 26 -
Power Down & Reset
The ADC and DAC of AK4620B are placed in power-down mode by bringing the PDN pin = “L”. Each digital filter is
also reset at the same time. The internal register values are initialized by bringing PDN pin to “L”. This reset should
always be done after power-up. As both control registers of the ADC and the DAC go to the reset state (RSTAD bit =
RSTDA bit = “0”), each register should be cleared after performing the reset. In the case of the ADC, an analog
initialization cycle starts after exiting the power-down or reset state. The output data (SDTO) is available after 516 cycles
of LRCK clock. This initialization cycle does not affect the DAC operation. Power down mode can be also controlled by
the registers (PWAD bit, PWDA bit).
The clocks can be stopped.
INITA: Initializing period of ADC analog section (516/fs).
PD: Power down state. The contents of all registers are held.
XXH, YYH: The current value in ATT registers.
FI: Fade in. After exiting power down and reset state, ATT value fades in.
FADE: After exiting power down and reset state, ATT value fades in/out.
(1) When RSTDA is “L” and OATT value is written to “XXH”, OATT value changes from FFH
to XXH according to fade operation.
(2) When PWDA is “L” and OATT value is written to “YYH”, OATT value changes from XXH
to YYH according to fade operation.
AOUT: Some pop noise may occur at “*”.
Figure 11. Reset & Power down sequence in serial mode
Power Supply
RSTAD(register)
RSTDA(register)
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
IATT
SDTO
OATT
AOUT
DAC Internal State
External Mute
Example
External clocks
PD Reset INITA
Normal
PD
INITA
Normal
00H
00H
→
XXH
XXH
00H 00H
→
XXH
XXH
“0”
“0”
FI
Output
FI
Output
PD
Reset
PD
Normal
Normal
FFH (1)
FFH
→
XXH
XXH
XXH(2)
XXH
→
YYH YYH
VCOM
Hi-z
FADE
Output
FADE
MCLK, LRCK, BICK
PDN pin
*
*
*
*
FFH
Hi-z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4620BVF | 24-Bit 192kHz Audio CODEC with IPGA |
| AK4626A | High Performance Multi-channel Audio CODEC |
| AK4626AVQ | High Performance Multi-channel Audio CODEC |
| AK4628A | High Performance Multi-channel Audio CODEC |
| AK4628AVQ | High Performance Multi-channel Audio CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4620BVF | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 192kHz Audio CODEC with IPGA |
| AK4620BVFPE2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4620BVFP-E2 | 功能描述:IC AUDIO CODEC 24BIT 30VSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2 |
| AK4621 | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 192kHz Stereo Audio CODEC |
| AK4621EF | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 192kHz Stereo Audio CODEC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。