參數(shù)資料
型號(hào): AK4569VN
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 20-Bit Stereo CODEC with IPGA & HP-AMP
中文描述: 20位立體聲編解碼器與單親遺傳算法
文件頁(yè)數(shù): 10/45頁(yè)
文件大?。?/td> 474K
代理商: AK4569VN
ASAHI KASEI
[AK4569]
MS0292-E-01
2005/07
- 10 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; AVDD, DVDD, HVDD = 2.5
3.6V: C
L
= 20pF)
Parameter
Master Clock Timing
Frequency
Pulse Width Low (Note 20)
Pulse Width High (Note 20)
AC Pulse Width (Note 21)
LRCK Timing
Frequency
Duty Cycle
Serial Interface Timing
(Note 22)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
” (Note 23)
BICK “
” to LRCK Edge (Note 23)
LRCK to SDTO(MSB)
BICK “
” to SDTO
SDTI Hold Time
SDTI Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
” to CCLK “
CCLK “
” to CSN “
Power-down & Reset Timing
PDN Pulse Width (Note 24)
PMADC “
” to SDTO valid (Note 25)
Note 20. Except AC coupling.
Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
ground. (Refer to Figure 4.)
Note 22. Refer to “Serial Data Interface”.
Note 23. BICK rising edge must not occur at the same time as LRCK edge.
Note 24. The AK4569 can be reset by bringing PDN= “L” to “H” only upon power up.
Note 25. This is the count of LRCK “
” from PMADC bit=”1”.
Symbol
fCLK
tCLKL
tCLKH
tACW
fs
Duty
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tPD
tPDV
min
2.048
0.4/fCLK
0.4/fCLK
0.4/fCLK
typ
max
24.576
48
55
80
80
Units
MHz
ns
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
8
45
44.1
325.5
130
130
50
50
50
50
200
80
80
40
40
150
50
50
150
2081
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