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參數(shù)資料
| 型號(hào)： | AK4566 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 20bit Stereo CODEC with built-in IPGA & HP-AMP |
| 中文描述： | 20位立體聲編解碼器內(nèi)置單親遺傳算法 |
| 文件頁數(shù)： | 23/45頁 |
| 文件大?。?/td> | 454K |
| 代理商： | AK4566 |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4566]
REV 0.5
2002/2
- 23 -
2) DAC
→
HP-amp
Power supply voltage for headphone amp is supplied from HVDD pin and centered around VCOM. Load resistance of
headphone output is min.20
. When PMHPL and PMHPR bit are “0”, headphone amplifiers are powered-down perfectly.
Then HPL and HPR pins are fixed to “L” (HVSS) and a capacitor of MUTET pin works to avoid pop noise.
Power Supply
(1)
>150ns
PDN pin
PMVCM bit
Clock Input
(4)
SDTI pin
PMDAC bit
DAC Internal
State
PD
Normal Operation
HPL/R pin
PMHPL/R bit
(5)
ATTL/R7-0 bit
00H(MUTE)
FFH(0dB)
(8) 1061/fs
(7) GD
PD
Normal Operation
00H(MUTE)
FFH(0dB)
(7)
(8)
(5)
(6)
(7) (8)
Don’t care
Don’t care
(6)
(7) (8)
00H(MUTE)
Don’t care
(9)
Don’t care
HPLMT,
HPRMT bit
(2) >0
PD
(3) >0
Figure 18. Power-up/down sequence of DAC and HP-amp
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
(3) PMDAC, PMHPL, PMHPR bits should be changed to “1” and HPLMT, HPRMT bits should be changed to “0” after
HPLMT, HPRMT, PMVCM bits are changed to “1”. Once PMHPL and PMHPR bits are changed to “1”, HPLMT
and HPRMT bits should be inverted from PMHPL and PMHPR bits respectively.
(4) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC= “0”, these clocks can be
stopped. Headphone amp can operate without these clocks.
(5) Rise time of headphone amp is determined by external capacitor of MUTET pin. When C=1μF,
Rise Time of Headphone Amp:
τ
= 100ms
(6) Fall time of headphone amp is determined by output capacitor for AC coupling. When C=100μF,
Fall Time of Headphone Amp:
τ
= 200ms
(7) Analog output corresponding to digital input has the group delay (GD) of 16.8/fs(=381μs@fs=44.1kHz).
(8) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(9) Power supply should be switched off after headphone amp is powered down (HPL/R pins become “L”).
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| AK4569 | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with IPGA & HP-AMP |
| AK4569VN | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with IPGA & HP-AMP |
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