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參數(shù)資料
| 型號： | AK4556VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 3V 192kHz 24Bit ツヒ CODEC |
| 中文描述： | 3V的192kHz 24位ツヒ編解碼器 |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 189K |
| 代理商： | AK4556VT |
ASAHI KASEI
[AK4556]
MS0559-E-00
2006/11
- 17 -
Digital High Pass Filter
The ADC has a Digital High Pass Filter (HPF) for DC-offset cancellation. The cut-off frequency of the HPF is 1Hz at
fs=48kHz and the frequency response at 20Hz is -0.12dB. It also scales with the sampling frequency (fs). The HPF is
controlled by CKS3-0 pins (Table 3). If the HPF setting (ON/OFF) is changed at operating, click noise occurs by
changing DC offset.
Power-down & Reset
The ADC and DAC are placed in power-down mode by bringing the PDN pin = “L”, and each digital filter is also reset at
the same time. These resets should always be done after power-up. For the ADC, an analog initialization cycle starts after
exiting the power-down mode. The output data, (SDTO) becomes available after 4131 cycles (@ Normal Speed) of
LRCK in master mode or 4134 cycles (@ Normal Speed) of LRCK in slave mode. During initialization, the ADC digital
data outputs of both channels are forced to a 2’s complement “0”. The ADC output data settles and correlates to the input
signal after the end of initialization (settling time is approximately equal to the group delay time.) The initialization cycle
does not affect the DAC operation.
PDN
Idle Noise
The clocks may be stopped.
ADC Internal
State
(1)
Normal Operation
Power-down
Init Cycle
Normal Operation
GD
GD
Clock In
MCLK,LRCK,BCLK
ADC In
(Analog)
Idle Noise
“0”data
ADC Out
(Digital)
Normal Operation
Power-down
Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD
External
Mute
Mute ON
GD
(2)
(2)
(4)
(3)
Notes:
(1) Slave mode (typ): 4134/fs @ Normal Speed, 8262/fs @ Double Speed, 16518/fs @ Quad Speed
Master mode (typ): 4131/fs @ Normal Speed, 8259/fs @ Double Speed, 16515/fs @ Quad Speed
(2) Click noise occurs at the “
↑↓
” of PDN signal. Mute the analog output externally if the click noise influences
system performance.
(3) LOUT/ROUT pins become Hi-Z at power-down.
(4) In master mode, LRCK and BICK output “L” at power-down.
Figure 9. Power-up/down Sequence
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