參數(shù)資料
型號(hào): AK4555VT
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi): Codec
英文描述: Low Power & Small Package 20bit ツヒ CODEC
中文描述: 低功耗
文件頁(yè)數(shù): 14/17頁(yè)
文件大?。?/td> 200K
代理商: AK4555VT
ASAHI KASEI
[AK4555]
MS0363-E-01
2005/08
- 14 -
Layout Pattern Example
AK4555 requires careful attention to power supply and grounding arrangements to optimize performance.
(Please refer to AKD4555 Evaluation Board layout pattern.)
1.
VDD pin should be supplied from analog power supply on system, and VSS pin should be connected to analog
ground on system. The AK4555 is placed on the analog ground plane, and near the analog ground and digital ground
split. And analog and digital ground planes should be only connected at one point. The connection point should be
near to the AK4555.
2.
VDD pin should be distributed from the point with low impedance of regulator etc.
3.
The series resistors are prevent on the clock lines to reduce overshoot and undershoot. To avoid digital noise
coupling to analog circuit in the AK4555, a 10pF ceramic capacitor on MCLK pin is connected with digital ground.
4.
0.1
μ
F ceramic capacitors of VDD-VSS pins and VCOM-VSS pins should be located as close to the AK4555 as
possible. And these lines should be the shortest connection to pins.
0.1u
+
Rch In
Lch In
Analog Supply
1.6
3.6V
10u
Controller
Digital Ground
Analog Ground
0.1u
VCOM
1
AINR
2
AINL
3
VSS
4
VDD
5
DEM0
6
DEM1
7
SDTO
8
16
15
14
13
12
11
10
9
AOUTR
AOUTL
PWADN
SCLK
MCLK
LRCK
SDTI
AK4555
Top View
PWDAN
10P
Reset &Power-down
Mode Control
+
+
51
51
51
51
51
Figure 7. Layout Pattern Example
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