參數(shù)資料
型號(hào): AK4554
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi): Codec
英文描述: Low Power & Small Package 16bit ツヒ CODEC
中文描述: 低功耗
文件頁(yè)數(shù): 9/17頁(yè)
文件大小: 205K
代理商: AK4554
ASAHI KASEI
[AK4554]
MS0325-E-01
2005/08
- 9 -
OPERATION OVERVIEW
System Clock Input
The AK4554 can be input MCLK=256fs, 384fs, 512fs, 768fs or 1024fs (fs is equal to or lower than 25kHz when MCLK
is 1024fs). The input clock applied to the MCLK pin as internal master clock is divided into 256fs automatically. When
MCLK is 1024fs, oversampling rate of D/A converter is automatically changed from 128fs to 256fs. The relationship
between the external clock applied to the MCLK input and the desired sample rate is defined in Table 1. The LRCK clock
input should be synchronized with MCLK.
The phase between these clocks does not matter. *fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4554 may
occur click noise.
All external clocks(MCLK, SCLK and LRCK) must be present unless PWADN=PWDAN= “L”. If these clocks are not
provided, the AK4554 may draw excess current and may not possibly operate properly because the device utilizes
dynamic refreshed logic internally.
fs
MCLK
256fs
384fs
512fs
8.0kHz
2.0480MHz
3.0720MHz
4.0960MHz
16.0kHz
4.0960MHz
6.1440MHz
8.1920MHz
32.0kHz
8.1920MHz
12.2880MHz
16.3840MHz
44.1kHz
11.2896MHz
16.9344MHz
22.5792MHz
48.0kHz
12.2880MHz
18.4320MHz
24.5760MHz
Table 1. System Clock Example
For low sampling rates, outband noise causes S/N of DAC to degrade. S/N is improved by setting MCLK to 1024fs. Table
2 shows S/N of DAC output.
fs
MCLK
8kHz
50kHz
256fs/384fs/512fs/768fs
8kHz
25kHz
1024fs
Table 2. Relationship among fs, MCLK frequency and S/N of DAC
SCLK
768fs
1024fs
8.1920MHz
16.3840MHz
N/A
N/A
N/A
32fs
64fs
6.1440MHz
12.2880MHz
24.5760MHz
33.8688MHz
36.8640MHz
0.2560MHz
0.5120MHz
1.0240MHz
1.4112MHz
1.5360MHz
0.512MHz
1.024MHz
2.048MHz
2.822MHz
3.072MHz
S/N(fs=8kHz, A-weighted)
84dB
90dB
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