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參數(shù)資料
| 型號： | AK4551VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | LOW POWER & SMALL PACKAGE 20BIT CODEC |
| 中文描述： | 低功耗 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 109K |
| 代理商： | AK4551VT |
ASAHI KASEI
[AK4551]
MS0029-E-00
2000/5
- 4 -
ANALOG CHARACTERISTICS
(Ta=25
°
C; VDD=2.5V; fs=44.1kHz; Signal Frequency=1kHz; SCLK=64fs; Measurement frequency=10Hz
～
20kHz;
unless otherwise specified)
Parameter
ADC Analog Input Characteristics:
Analog Source Impedance=470
(
Note 2
)
Resolution
S/(N+D) (-0.5dB Input)
D-Range (-60dB Input, A-weighted)
S/N (A-weighted)
Interchannel Isolation
Interchannel Gain Mismatch
Input Voltage (
Note 3
)
Input Resistance
Power Supply Rejection (
Note 4
)
DAC Analog Output Characteristics:
Resolution
S/(N+D)
D-Range (-60dB Output, A-weighted)
S/N (A-weighted)
Interchannel Isolation
Interchannel Gain Mismatch
Output Voltage (
Note 3
)
Load Resistance
Load Capacitance
Power Supply Rejection (
Note 4
)
Power Supplies
Power Supply Current
DA
Power down (
Note 5
)
PWAD = “L”, PWDA = “L”
Power Consumption
AD+DA
AD
DA
Power down (
Note 5
)
PWAD = “L”, PWDA = “L”
Note 2. The offset of ADC is removed by internal HPF.
Note 3. Input /Output of ADC and DAC scales with VDD voltage. 0.6 X VDD (typ).
Note 4. PSR is applied to VDD with 1kHz, 50mV.
Note 5. In case of power-down mode, all digital input including clocks pins (MCLK, SCLK and LRCK) are held VDD or
VSS. But PWAD and PWDA pins are held VSS.
min
typ
max
Units
20
0.5
1.65
Bits
dB
dB
dB
dB
dB
Vpp
k
dB
72
82
82
80
1.35
50
82
89
89
95
0.2
1.50
100
35
20
0.5
1.65
30
Bits
dB
dB
dB
dB
dB
Vpp
k
pF
dB
75
86
86
80
1.35
10
85
92
92
95
0.2
1.50
50
AD+DA
AD
PWAD = “H”, PWDA =
“H” PWAD = “H”, PWDA =
“L” PWAD = “L”, PWDA = “H”
10
5.6
5.6
10
15
8.4
8.4
50
37.5
21
21
125
mA
mA
mA
uA
PWAD = “H”, PWDA = “H”
PWAD = “H”, PWDA = “L”
PWAD = “L”, PWDA = “H”
25
14
14
25
mW
mW
mW
uW
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