參數(shù)資料
型號(hào)： AK4541
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： AC’97 Rev 2.1 Multimedia Audio CODEC
中文描述： AC\u0026#39;97音效活2.1多媒體音頻編解碼器
文件頁(yè)數(shù)： 8/31頁(yè)
文件大?。?/td> 383K
代理商： AK4541
[ASAHI KASEI]
[AK4541]
<M0047-E-01>
1999/01
- 8 -
n
Power On
Note that a AK4541 must be in cold reset at power on and RESET# must be low until master clock becomes stable,
or a reset must be done once master clock is stable. AVdd or DVdd can be powered from independent supplies.
BIT_CLK
Initialize Registers
start up crystal oscillation
SYNC=L
SDATA_OUT=L
RESET#
Vdd
T
rst2clk
When using the AK4541 in the multiple codec mode, all codecs connected to the AC-link are waken up at the same
time. A common reset line should be used to insure clock synchronization after power up.
n
Cold Reset Timing
Note that both SDATA_OUT and SYNC must be low at the rising edge of RESET# for a cold reset to occur.
The AK4541 initializes all registers including the Powerdown Control Registers, BIT-CLK is reactivated and each
analog output is in Hi-Z state except for PC Beep while RESET# pin is low.
The PC Beep is directly routed to L
& R line outputs when AK4541 is in Cold Reset.
This is done to allow system sounds to be passed to speaker
removing for an internal redundant speaker.
At the rising edge of RESET#, the AK4541 initiates the initialization of analog circuit, which takes 516fs cycles.
After that, the mixer of the AK4541 is ready for normal operation.
Status bit in the slot 0 is 0 (not ready) when the AK4541 is in RESET period (L) or in initialization process.
After initialization cycles, the status bit goes to 1 indicating a ready condition.
BIT_CLK
V
IL
RESET#
T
rst2clk
T
rst_low
SYNC=L
SDATA_OUT=L
When the AK4541 is used under the multiple codec configuration and when cold reset is issued, all AK4541
connected to the AC-link will execute a cold reset concurrently.
n
Warm Reset
The AK4541 initiates a warm reset process by receiving a single pulse on the sync(Pin10). The AK4541 then clears
PR4 bit and PR5 bit in the Powerdown Control Register. However, warm reset does not influence PR0
～
PR3 or
PR6,7 bits in Powerdown Control Register(26h). Note that SYNC signal should synchronize with BIT_CLK after
AK4541 starts to output BIT_CLK clock. And if an external clock is used, an external clock should be supplied
before issuing a sync pulse for warm reset.
T
sync2clk
T
sync_high
V
IH
BIT_CLK
SYNC
相關(guān)PDF資料
PDF描述
AK4543 AC’97 Rev 2.1 Multimedia Audio CODEC
AK4543VQ AC’97 Rev 2.1 Multimedia Audio CODEC
AK4544A AC97 MULTIMEDIA AUDIO CODEC WITH SRC
AK4544AVQ CABLE ASSEMBLY; BNC MALE TO N MALE; 50 OHM, RG223/U COAX, DOUBLE SHIELDED; 36" CABLE LENGTH
AK4544 AC97 MULTIMEDIA AUDIO CODEC WITH SRC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4541VQ 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
AK4543 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
AK4543VQ 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
AK4544 制造商:AKM 制造商全稱:AKM 功能描述:AC97 MULTIMEDIA AUDIO CODEC WITH SRC
AK4544A 制造商:AKM 制造商全稱:AKM 功能描述:AC97 MULTIMEDIA AUDIO CODEC WITH SRC
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