參數(shù)資料
型號(hào)： AK4528VF
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC
中文描述： 高性能24位96kHz的音頻編解碼器
文件頁(yè)數(shù)： 20/29頁(yè)
文件大?。?/td> 284K
代理商： AK4528VF
ASAHI KASEI
[AK4528]
MS0011-E-00
2000/1
- 20 -
n
Register Definitions
Addr
00H
Register Name
Power Down Control
default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
D1
D0
PWVR
1
PWAD
1
PWDA
1
PWDA: DAC power down
0: Power down
1: Power up
Only DAC section is powered down by “0” and then the AOUTs go Hi-Z immediately. The OATTs also go
“00H”. But the contents of all register are not initialized and enabled to write to the registers.
After exiting the power down mode, the OATTs fade in the setting value of the control register (04H &
05H). The analog outputs should be muted externally as some pop noise may occur when entering to and
exiting from this mode.
PWAD: ADC power down
0: Power down
1: Power up
Only ADC section is powered down by “0” and then the SDTO goes “L” immediately. The contents of all
register are not initialized and enabled to write to the registers.
After exiting the power down mode, ADC outputs “0” during first 516 LRCK cycles.
PWVR: Vref power down
0: Power down
1: Power up
All sections are powered down by “0” and then both ADC and DAC do not operate. The contents of all
register are not initialized and enabled to write to the registers. When PWAD and PWDA go “0” and PWVR
goes “1”, only VREF section can be powered up.
Addr
01H
Register Name
Reset Control
default
D7
TE7
0
D6
TE6
0
D5
TE5
0
D4
TE4
0
D3
0
0
D2
0
0
D1
D0
RSTADN
0
RSTDAN
0
TE7-4:
Test Control Register Enable
Must be fixed to “0000”.
RSTDAN: DAC reset
0: Reset
1: Normal Operation
The internal timing is reset by “0” and then the AOUTs go VCOM voltage immediately. The OATTs also go
“00H”. But the contents of all register are not initialized and enabled to write to the registers. After exiting
the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The analog
outputs should be muted externally as some pop noise may occur when entering to and exiting from this
mode.
RSTDAN: ADC reset
0: Reset
1: Normal Operation
The internal timing is reset by “0” and then SDTO goes “L” immediately. But the contents of all register are
not initialized and enabled to write to the register.
After exiting the power down mode, ADCs output “0” during first 516 LRCK cycles.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AK4528VM 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 24Bit 96kHz Audio CODEC
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AK4529 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Multi-channel Audio CODEC
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