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參數(shù)資料
| 型號： | AK4525 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 20BIT STEREO ADC & DAC WITH X TAL OSC |
| 中文描述： | 20位立體聲ADC |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 152K |
| 代理商： | AK4525 |
ASAHI KASEI
[AK4525]
MS0053-E-00
2000/9
- 7 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; VA=4.5
～
5.5V; VD=3.1
～
5.5V; C
L
=20pF)
Parameter
Master Clock Timing
256fs
384fs
512fs
MCKO Output
Frequency
Duty Cycle
Rise Time (Note 15)
Fall time (Note 15)
LRCK Timing
Frequency
Duty Cycle
Serial Interface Timing
Slave mode
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “
↑
” (Note 16)
SCLK “
↑
” to LRCK Edge (Note 16)
LRCK to SDTO (MSB)
SCLK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Master mode
SCLK Frequency
SCLK Duty
SCLK “
↓
” to LRCK
SCLK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Reset Timing
PDN Pulse Width (Note 17)
PDN “
↑
” to SDTO valid (Note 18)
Symbol
min
typ
max
Units
8.192
12.288
16.384
12.288
18.432
24.576
MHz
MHz
MHz
fMCK
dMCK
tR
tF
8.192
50
24.576
5
5
MHz
%
ns
ns
fs
dfs
32
45
48
55
kHz
%
tSCK
tSCKL
tSCKH
tLRS
tSLR
tLRM
tSSD
tSDH
tSDS
320
65
65
45
45
40
25
40
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
fSCK
dSCK
tMSLR
tSSD
tSDH
tSDS
-20
40
25
64fs
50
20
70
Hz
%
ns
ns
ns
ns
tPD
tPDV
150
516
ns
1/fs
Notes: 15. VD=3.1V, 0.8
～
2.0V.
16. SCLK rising edge must not occur at the same time as LRCK edge.
17. The AK4525 can be reset by bringing PDN “L”. When the state of CMODE changes during operation, the
AK4525 should be reset by PDN. PDN should be held “L” for 5ms to allow the X’tal oscillation to begin at
power-up.
18. These cycles are the number of LRCK rising from PDN rising.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AK4525VF | 制造商:AKM 制造商全稱:AKM 功能描述:20BIT STEREO ADC & DAC WITH X TAL OSC |
| AK4527B | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.D FOR AK4527B |
| AK4527BVQ | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC |
| AK4528 | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC |
| AK4528_04 | 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 24Bit 96kHz Audio CODEC |
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