參數(shù)資料
型號: AK4520
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 100dB 20Bit Stereo ADC & DAC
中文描述: 100dB的20位立體聲ADC
文件頁數(shù): 12/19頁
文件大?。?/td> 198K
代理商: AK4520
ASAHI KASEI
[AK4520A]
0163-E-00
1997/3
- 12 -
Power-Down & Reset
The ADC and DAC of AK4520A are placed in the power-down mode by bringing each power down pin, PWAD
PWDA "L" independently and each digital filter is also reset at the same time. This reset should always be done
after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode.
Therefore, the output data, SDTO becomes available after 516 cycles of LRCK clock. This initialization cycle
does not affect the DAC operation.
Figure 5 shows the power-up sequence when the DAC is powered up before the ADC power-up.
1
{
The analog part of ADC is initialized after exiting the power-down state.
Digital output corresponding to analog input and analog output corresponding to digital input have
the group delay(GD).
A/D output is "0" data at the power-down state.
Click noise occurs at the end of initialization of the analog part. Please mute the digital output
externally if the click noise influences system application. Required muting time depends on the
configuration of the input buffer circuits.
Figure 6: 1s
Figure 9: 200ms
Click noise occurs at the edge of PWDA.
Please mute the analog output externally if the click noise(
5
{
) influences system application.
2
{
3
{
4
{
5
{
6
{
Figure 5 . Power-up sequence
相關(guān)PDF資料
PDF描述
AK4520A 100dB 20Bit Stereo ADC & DAC
AKD4522 EVALUATION BOARD REV.A FOR AK4522
AKD4523 EVALUATION BOARD REV.A FOR AK4523
AKD4524 EVALUATION BOARD REV.A FOR AK4524
AKD4527B EVALUATION BOARD REV.D FOR AK4527B
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4520A 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.B FOR AK4520A
AK4520A-VF 制造商:AKM 制造商全稱:AKM 功能描述:100dB 20Bit Stereo ADC & DAC
AK4522 制造商:AKM 制造商全稱:AKM 功能描述:20Bit Stereo ΔΣ ADC & DAC
AK4522_12 制造商:AKM 制造商全稱:AKM 功能描述:20Bit Stereo ΔΣ ADC & DAC
AK4522VF 制造商:AKM 制造商全稱:AKM 功能描述:20BIT STEREO ADC & DAC