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參數(shù)資料
| 型號： | AK4397EQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | High Performance Premium 32-Bit DAC |
| 中文描述： | 優(yōu)質(zhì)高性能32位DAC |
| 文件頁數(shù)： | 8/37頁 |
| 文件大?。?/td> | 513K |
| 代理商： | AK4397EQ |
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[AK4397]
MS0616-E-00
2007/05
- 8 -
ANALOG CHARACTERISTICS
(Ta=25
°
C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS; Input data=24bit;
R
L
≥
1k
Ω
; BICK=64fs; Input Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth =
20Hz ~ 20kHz; External Circuit: Figure 18; unless otherwise specified.)
Parameter
Resolution
Dynamic Characteristics
(Note 5)
fs=44.1kHz
BW=20kHz
60dBFS
fs=96kHz
BW=40kHz
60dBFS
BW=80kHz
60dBFS
Dynamic Range (
60dBFS with A-weighted) (Note 6)
S/N (A-weighted) (Note 7)
Interchannel Isolation (1kHz)
DC Accuracy
Interchannel Gain Mismatch
Gain Drift (Note 8)
Output Voltage (Note 9)
Load Capacitance
Load Resistance (Note 10)
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD + VDDL/R
DVDD (fs
≤
96kHz)
DVDD (fs = 192kHz)
AVDD+DVDD
Power Supply Rejection (Note 12)
Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. By Figure 18. External LPF Circuit Example 2.101dB at 16bit data and 118dB at 20bit data.
Note 7. By Figure 18. External LPF Circuit Example 2. S/N does not depend on input bit length.
Note 8. The voltage on (VREFHL/R
VREFLL/R) is held +5V externally.
Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R
VREFLL/R).
AOUT (typ.@0dB) = (AOUT+)
(AOUT
) =
±
2.8Vpp
×
(VREFHL/R
VREFLL/R)/5.
Note 10. Regarding Load Resistance, AC load is 1 k
Ω
(min) with DC cut capacitor. Please refer to Figure 18. DC load is
1.5k
Ω
(min) without DC cut capacitor. Please refer to Figure 17. Load Resistance value defines apposite to
ground voltage. Analog performance is sensitive to capacitive load that is connected output pin. Therefore
capacitive load must be minimized.
Note 11. In the power-down mode. P/S pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held VSS4.
Note 12. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFHL/R pin is held +5V.
min
-
typ
-
max
24
Units
Bits
0dBFS
-
-
-
-
103
57
100
54
100
54
51
120
120
110
93
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0dBFS
THD+N
fs=192kHz
BW=40kHz
0dBFS
60dBFS
114
114
100
-
-
0.15
20
±
2.8
-
-
0.3
-
±
2.95
25
-
dB
ppm/
°
C
Vpp
pF
k
Ω
±
2.65
-
1
-
-
-
-
-
32
21
27
10
50
47
-
41
100
-
mA
mA
mA
μ
A
dB
Power down (PDN pin = “L”) (Note 11)
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