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參數(shù)資料
| 型號(hào)： | AK4386VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 100DB 96KHZ 24 BIT 2CH |
| 中文描述： | 100dB的96kHz的24位二通 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 129K |
| 代理商： | AK4386VT |
ASAHI KASEI
[AK4386]
MS0280-E-00
2003/12
- 12 -
(1) Power down by PDN pin
PDN
Normal Operation
Internal
State
Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(2)
(4)
External
MUTE
(6)
(4)
(2)
Mute ON
(3)
(5)
Don’t care
(1)
Notes:
(1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7
μ
F is attached between VCOM pin and
VSS.)
(2) The analog output corresponding to digital input has the group delay (GD).
(3) When PDN pin = “L”, the analog output is Hi-Z.
(4) Click noise occurs in 3
～
4LRCK at both edges (
↑
↓
) of PDN signal. This noise is output even if “0” data is input.
(5) The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = “L”).
(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example
is shown in this figure.
Figure 5. Power-down/up sequence example 1
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