參數(shù)資料
型號(hào)： AK4384
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 106dB 192kHz 24-Bit 2ch DAC
中文描述： 一零六分貝192kHz的24位2通道數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 9/22頁(yè)
文件大小： 241K
代理商： AK4384
ASAHI KASEI
[AK4384]
MS0176-E-00
2002/09
- 9 -
OPERATION OVERVIEW
n
System Clock
The external clocks, which are required to operate the AK4384, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “
↑
”), the AK4384 is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the
appropriate frequency (Table 6), it is not necessary to set DFS0/1.
In parallel mode, the sampling speed can be set by only ACKS pin. The internal DFS0 andDFS1 bits are fixed to “0”.
Therefore, when ACKS pin is “L”, the AK4384 operates in Normal Speed Mode. The AK4384 operates in Auto Setting
Mode at ACKS = “H”. In parallel mode, the AK4384 does not support 128fs and 192fs of Double Speed Mode.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4384 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4384 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4384 should be reset by PDN=
“L” after threse clocks are provided. If the external clocks are not present, the AK4384 should be in the power-down mode
(PDN= “L”). After exiting reset at power-up etc., the AK4384 is in the power-down mode until MCLK and LRCK are
input.
DFS1
DFS0
0
0
Normal Speed Mode
0
1
Double Speed Mode
1
0
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
MCLK
fs
256fs
384fs
512fs
32.0kHz
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz
44.1kHz
11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
48.0kHz
12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
MCLK
fs
128fs
192fs
88.2kHz
11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
96.0kHz
12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
Sampling Rate (fs)
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Default
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
768fs
1152fs
N/A
N/A
BICK
64fs
5.6448MHz
6.1440MHz
256fs
384fs
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