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參數(shù)資料
| 型號： | AK4381 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | AB 3C 3#16 PIN RECP |
| 中文描述： | 108DB 192kHz的24位2聲道數(shù)模轉換器 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 232K |
| 代理商： | AK4381 |
ASAHI KASEI
[AK4381]
MS0152-E-00
2002/5
- 9 -
OPERATION OVERVIEW
n
System Clock
The external clocks, which are required to operate the AK4381, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “
↑
”), the AK4381 is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the
appropriate frequency (Table 6), it is not necessary to set DFS0/1.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4381 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4381 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4381 should be reset by PDN=
“L” after threse clocks are provided. If the external clocks are not present, the AK4381 should be in the power-down mode
(PDN= “L”). After exiting reset at power-up etc., the AK4381 is in the power-down mode until MCLK and LRCK are
input.
DFS1
DFS0
0
0
Normal Speed Mode
0
1
Double Speed Mode
1
0
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
MCLK
fs
256fs
384fs
32.0kHz
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz
44.1kHz
11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
48.0kHz
12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
MCLK
fs
128fs
192fs
88.2kHz
11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
96.0kHz
12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
MCLK
fs
128fs
176.4kHz
22.5792MHz
33.8688MHz
192.0kHz
24.5760MHz
36.8640MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
Sampling Rate (fs)
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Default
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
512fs
768fs
BICK
64fs
5.6448MHz
6.1440MHz
256fs
384fs
BICK
64fs
192fs
11.2896MHz
12.2880MHz
相關PDF資料 |
PDF描述 |
|---|---|
| AK4381VT | AB 3C 3#16 PIN WALL MT RECEP |
| AKD4382 | Circular Connector; No. of Contacts:22; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:12-35 RoHS Compliant: No |
| AKD4386 | ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
| AK4386 | 100DB 96KHZ 24 BIT 2CH |
| AK4386VT | 100DB 96KHZ 24 BIT 2CH |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4381VT | 制造商:AKM 制造商全稱:AKM 功能描述:108DB 192KHZ 24-BIT 2CH DAC |
| AK4381VTP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:5V 108DB DAC |
| AK4382 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.A FOR AK4382 |
| AK4382A | 制造商:AKM 制造商全稱:AKM 功能描述:112dB 192kHz 24-Bit 2ch DAC |
| AK4382AVT | 制造商:AKM 制造商全稱:AKM 功能描述:112dB 192kHz 24-Bit 2ch DS DAC |
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