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參數(shù)資料
| 型號： | AK4363VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 96kHz 24Bit DAC with PLL |
| 中文描述： | 96kHz的24位DAC，帶有鎖相環(huán) |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 248K |
| 代理商： | AK4363VF |
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ASAHI KASEI
[AK4363]
MS0015-E-01
2000/07
- 20 -
n
Reset function
When RSTN = “0”, the DAC is powered down but the internal register values are not initialized. The analog outputs go
to VCOM voltage and DZF pin goes to “H”. Figure 8 shows the sequence of reset by RSTN bit.
Internal
State
RSTN bit
Digital Block Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCKI,LRCK,BICK
(1)
(3)
DZF
(3)
(1)
(2)
Normal Operation
2/fs(5)
Internal
RSTN bit
2~3/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges(“
↑
↓
”) of the internal timing of RSTN bit. This noise is output even if “0” data
is input.
(4) The external clocks (MCKI, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pin goes to “H” when the RSTN bit becomes “0”, and goes to “L” at 4~5/fs after RSTN bit becomes “1”.
(6) There is a delay, 2~3/fs from RSTN bit “1” to the internal RSTN “1”.
Figure 8. Reset sequence example
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