參數(shù)資料
型號(hào): AK4357VQ
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 192kHz 24-Bit 6ch DAC with DSD Input
中文描述: 192kHz的24位6通道DAC,具有DSD輸入
文件頁數(shù): 10/27頁
文件大小: 195K
代理商: AK4357VQ
ASAHI KASEI
[AK4357]
MS0088-E-02
2002/07
- 10 -
OPERATION OVERVIEW
n
D/A Conversion Mode
The AK4357 can perform D/A conversion for both PCM data and DSD data. When DSD mode, DSD data can be input from
DCLK, DSDL1-3 and DSDR1-3 pins. When PCM mode, PCM data can be input from BICK, SDTI1-3 and LRCK pins.
PCM/DSD mode changes by DSDM pin or D/P bit, DSDM pin setting and D/P bit setting are ORed internal. When
PCM/DSD mode changes by DSDM pin or D/P bit, the AK4357 should be reset by RSTN bit, PW bit (PW1=PW2=PD3=”0”)
or PDN pin. It takes about 2/fs to 3/fs to change the mode.
DSDM pin
D/P bit
0
L
1
0
H
1
Table 1. DSD/PCM Mode Control
n
System Clock
1) PCM Mode
The external clocks, which are required to operate the AK4357, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter
and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”:
Register 00H), the sampling speed is set by DFS0/1(Table 2). The frequency of MCLK at each sampling speed is set
automatically. (Table 3~5). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically
(Table 6), and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to set DFS0/1.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4357 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4357 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4357 should be reset by PDN= ”L”
after threse clocks are provided. If the external clocks are not present, the AK4357 should be in the power-down mode
(PDN= ”L”). After exiting reset(PDN = “
”) at power-up etc., the AK4357 is in the power-down mode until MCLK is input.
DSD interface signals (DCLK, DSDL1-3, DSDR1-3) are fixed to “H” or “L”.
DAC Output
PCM
DSD
DSD
DSD
DFS1
DFS0
Sampling Rate (fs)
0
0
0
1
Normal Speed Mode
Double Speed Mode
8kHz~48kHz
60kHz~96kHz
Default
1
0
Quad Speed Mode
120kHz~192kHz
Table 2. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
BICK
64fs
256fs
384fs
512fs
768fs
8.1920MHz
11.2896MHz
12.2880MHz
12.2880MHz
16.9344MHz
18.4320MHz
16.3840MHz
22.5792MHz
24.5760MHz
24.5760MHz
33.8688MHz
36.8640MHz
2.0480MHz
2.8224MHz
3.0720MHz
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
相關(guān)PDF資料
PDF描述
AK4358 192 KHZ 24 BIT 8 CH DAC WITH DSD INPUT
AKD4358 Circular Connector; No. of Contacts:22; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:12-35 RoHS Compliant: No
AK4358VQ 192 KHZ 24 BIT 8 CH DAC WITH DSD INPUT
AK4359 192 KHZ 24 BIT 8CH DAC
AKD4359 Circular Connector; No. of Contacts:22; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:12-35 RoHS Compliant: No
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