參數(shù)資料
型號: AK4353VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 96kHz 24BIT DAC WITH DIT
中文描述: 96kHz的24位DAC,具有動態(tài)網(wǎng)
文件頁數(shù): 16/33頁
文件大小: 254K
代理商: AK4353VF
ASAHI KASEI
[AK4353]
MS0016-E-01
2000/07
- 16 -
LRCK
BICK
(64fs)
SDTI
0
22
1
2
24
31
0
1
31
0
1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data
Rch Data
23
30
22
2
24
23
30
22
1
0
Don’t care
23
22
23
Fig
ure
4. Mode 4 Timing
LRCK
BICK
(64fs)
SDTI
0
3
1
2
24
31
0
1
31
0
1
23:MSB, 0:LSB
22
1
0
Don’t care
23
Lch Data
Rch Data
23
25
3
2
24
23
25
22
1
0
Don’t care
23
BICK
(32fs)
SDTI
0
3
1
2
12
15
0
1
0
1
23
22
13
8
11
14
2
12
11
10
9
13
3
12
15
11
14
13
23
22
13
8
12
11
10
9
23
8
23
Figure 5. Mode 5 Timing
n
Data Transmission Format
Data input via SDTI pin is formatted in digital interface format and output via TX pin. Data transmitted on the TX output
is formatted in blocks as shown in figure 6. Each block consists of 192 frames. A frame of data contains two sub-frames.
A sub-frame consists of 32 bits of information. Each data bit received is coded using a bi-phase mark encoding as a two
binary state symbol. The preambles violate bi-phase encoding so they may be differentiated from data. In bi-phase
encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. For a logic
0, the second state of the symbol is the same as the first state. For a 1, the second state is the opposite of the first. Figure
7 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
Frame 191
Frame 0
Frame 1
Sub-frame
Sub-frame
M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2
Figure 6. Block format
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