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參數(shù)資料
| 型號： | AK4352 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 2V & LOW POWER MULTI-BIT DAC |
| 中文描述： | 2V的 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 88K |
| 代理商： | AK4352 |
ASAHI KASEI
[AK4352]
M0040-E-02
2000/11
- 9 -
Lch
Rch
15
14
1
0
15
17
16
3
2
17
1
0
LRCK
BICK
SDATA
16bit
SDATA
18bit
Don’t
care
Don’t
care
16
3
2
17
1
0
15
14
1
0
Don’t
care
Don’t
care
* BICK needs 32fs or 36fs
or more than 36fs.
Figure 4. Mode 3 Timing
n
De-emphasis filter
The AK4352 includes the digital de-emphasis filter (tc=50/15
μ
s) by IIR filter. This filter corresponds to 44.1kHz
sampling. The de-emphasis is enabled by setting DEM pin “H”.
n
Power-down
The AK4352 is placed in the power-down mode by bringing PD pin “L” and the anlog outputs are floating(Hi-Z).
Figure 5 shows an example of the system timing at the power-down and power-up.
Normal Operation
Internal
State
PD
Power-down
Normal Operation
GD
GD
“0”data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1)
(2)
(4)
External
Mute
(5)
(1)
(3)
(3)
Mute On
Figure 5. Power-down/up sequence example
Notes:
(1) Analog output corresponding to digital input have the group delay (GD).
(2) Analog outputs are floating(Hi-Z) at the power-down mode.
(3) Click noise occures at the edges(“
↑
↓
”) of the falling edge of PD signal.
(4) When the external clocks(MCLK,BICK,LRCK) are stopped, the AK4352 should be in the power-down
mode.
(5) Please mute the analog output externally if the click noise(3) influences system application.
The timing example is shown in this figure.
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| AK4353VF | 96kHz 24BIT DAC WITH DIT |
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|---|---|
| AK4352VT | 制造商:AKM 制造商全稱:AKM 功能描述:2V & LOW POWER MULTI-BIT DAC |
| AK4352VTP | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4353 | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz 24BIT DAC WITH DIT |
| AK4353VF | 制造商:AKM 制造商全稱:AKM 功能描述:96kHz 24BIT DAC WITH DIT |
| AK4353VF-E2 | 制造商:Asahi Kasei Microsystems Co LTD 功能描述:SERIAL INPUT LOADING, 24-BIT DAC, VSOP-24 |
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