
ASAHI KASEI 
[AK4346] 
MS0531-E-00 
2006/07 
- 3 - 
PIN/FUNCTION 
No. 
1 
Pin Name 
MCLK 
I/O 
I 
Function 
Master Clock Input 
   An external TTL clock should be input on this pin. 
Audio Serial Data Clock 
DAC1 Audio Serial Data Input 
L/R Clock 
Reset Mode 
   When at “L”, the AK4346 is in reset mode. 
The AK4346 must be reset once upon power-up. 
Soft Mute in parallel control mode 
“H”: Enable, “L”: Disable 
Chip Select in serial 3-wire mode 
Chip Address in serial I2C mode 
Auto Setting Mode in parallel control mode 
   “L”: Manual Setting Mode,    “H”: Auto Setting Mode 
Control Data Clock in serial 3-wire control mode  
Control Data Clock in serial I2C control mode 
Audio Data Interface Format in parallel control mode 
Control Data Input in serial 3-wire control mode  
Control Data in serial I2C control mode 
DAC2 Audio Serial Data Input  
DAC3 Audio Serial Data Input  
Test pin – connect to ground.  
Audio Data Interface Format 
Chip Address in serial control mode 
De-emphasis Filter Enable 
Digital Power Supply, +2.7
~
+3.6V 
Digital Ground 
μ
P I/F Mode Select in serial control mode 
“L”: 3-wire Serial, “H”: I
2
C Bus 
De-emphasis Filter Enable in parallel control mode 
Test pin – leave this pin floating. 
Test pin – leave this pin floating. 
DAC3 Right Channel Analog Output 
DAC3 Left Channel Analog Output 
DAC2 Right Channel Analog Output 
DAC2 Left Channel Analog Output 
Parallel/Serial Control Mode Select                        (Internal pull-up pin) 
   “L”: Serial control mode, “H”: Parallel control mode  
DAC1 Right Channel Analog Output 
DAC1 Left Channel Analog Output 
Common Voltage, AVDD/2 
   Normally connected to AVSS with a 0.1
μ
F ceramic capacitor in parallel with a 
10
μ
F electrolytic cap. 
Analog Ground 
Analog Power Supply, +2.7
~
+3.6V 
TDM I/F Format Mode in parallel control mode  (Internal pull-down pin) 
  “L”: Normal mode, “H”: TDM 256 mode 
Data Zero Input Detect in serial control mode 
Data Zero Input Detect 
Note: All input pins except P/S and TDM0 pins should not be left floating. 
2 
3 
4 
5 
BICK 
SDTI1 
LRCK 
RSTB 
I 
I 
I 
I 
SMUTE 
I 
CSN 
CAD0 
ACKS 
I 
I 
I 
6 
CCLK 
SCL 
DIF0 
CDTI 
SDA 
SDTI2 
SDTI3 
TST1 
DIF1 
CAD1 
DEM0 
DVDD 
DVSS 
I2C 
I 
I 
I 
7 
8 
I/O 
I 
I 
I 
I 
I 
I 
9 
10 
11 
12 
13 
14 
15 
16 
DEM1 
TST2 
TST3 
ROUT3 
LOUT3 
ROUT2 
LOUT2 
P/S 
I 
- 
- 
O 
O 
O 
O 
I 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 
ROUT1 
LOUT1 
VCOM 
O 
O 
O 
27 
28 
29 
AVSS 
AVDD 
TDM0 
- 
- 
I 
DZF2 
DZF1 
O 
O 
30