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參數(shù)資料
| 型號： | AK4340 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192kHz 24-Bit Stereo DAC with 2Vrms Output |
| 中文描述： | 192kHz的24位立體聲DAC 2Vrms的輸出 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 265K |
| 代理商： | AK4340 |
ASAHI KASEI
AKM CONFIDENTIAL
[AK4340]
Rev.0.6
2005/11
- 10 -
OPERATION OVERVIEW
System Clock
The AK4340 requires MCLK, BICK and LRCK external clocks. The master clock (MCLK) should be synchronized with
LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma
modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the
sampling speed is set by DFS0/1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table
2) After exiting reset (PDN pin = “
↑
”), the AK4340 is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”:
Default), as MCLK frequency is detected automatically (Table 3), and the internal master clock becomes the appropriate
frequency (Table 4), it is not necessary to set DFS0/1.
In parallel control mode, the sampling speed can be set by only ACKS pin. The internal DFS0 and DFS1 bits are fixed to
“0”. Therefore, when ACKS pin is “L”, the AK4340 operates in Normal Speed Mode. The AK4340 operates in Auto
Setting Mode at ACKS pin = “H”. In parallel control mode, the AK4340 does not support 128fs and 192fs of Double
Speed Mode.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4340 is in the normal operation
mode (PDN pin = “H”). If these clocks are not provided, the AK4340 may draw excess current and may fall into
unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4340 should be
reset by PDN pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4340 should be in
the power-down mode (PDN pin = “L”). After exiting reset at power-up etc., the AK4340 is in the power-down mode
until MCLK and LRCK are input.
DFS1
DFS0
0
0
Normal Speed Mode
0
1
Double Speed Mode
1
0
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
(kHz)
DFS1
DFS0
Speed
fs
128fs
192fs
0
0
32.0
-
-
0
0
44.1
-
-
0
0
48.0
-
-
0
1
88.2
11.2896
16.9344
22.5792
0
1
96.0
12.2880
18.4320
24.5760
1
0
176.4
22.5792
33.8688
1
0
192.0
24.5760
36.8640
Table 2. System Clock Example (Manual Setting Mode)
Sampling Rate (fs)
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Default
MCLK(MHz)
BICK
(MHz)
64fs
2.0480
2.8224
3.0720
5.6448
6.1440
11.2896
12.2880
Sampling
256fs
8.1920
11.2896
12.2880
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
-
-
512fs
16.3840
22.5792
24.5760
-
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
1152fs
36.8640
-
-
-
-
-
-
Normal
Double
-
-
Quad
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