參數(shù)資料
型號: AK4317
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 18BIT SCF DAC WITH ATT & MIXER
中文描述: 18位超臨界DAC,具有先進(jìn)交通運(yùn)輸
文件頁數(shù): 3/19頁
文件大?。?/td> 171K
代理商: AK4317
ASAHI KASEI
[AK4317]
0172-E-01
1997/5
- 3 -
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
DVDD
-
Digital Power Supply
2
3
DVSS
PD
-
I
Digital Ground Pin
Power-Down Mode Pin
When at "L", the AK4317 is in power-down mode and is held in reset.
The AK4317 should always be reset upon power-up.
Digital Input Format Pin (Internal Pull-down pin)
Master Clock Input Pin
Digital Input Format Pin (Internal Pull-down pin)
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
2's complement MSB-first data is input on this pin.
L/R Clock Pin
Control Data Input Pin
Must be tied to "H" or "L" if this pin is not used.
Control Clock Pin
Must be tied to "H" or "L" if this pin is not used.
Chip Select Pin
Must be tied to "H" if this pin is not used.
Test Pin
Must be left floating.
Soft Mute Pin
When this pin goes "H", soft mute cycle is initiated.
When returning "L", the output mute releases.
De-emphasis Enable Pin (Internal Pull-down pin)
Master Clock Select Pin
MCLK=256fs,"H": MCLK=384fs
Channel 1 analog output pin
4
5
6
7
8
DIF0
MCLK
DIF1
BICK
SDATA
I
I
I
I
I
9
10
LRCK
CDATA
I
I
11
CCLK
I
12
CS
I
13
TST2
O
14
SMUTE
I
15
16
DEM
CKS
I
I
17
AOUT1
O
18
19
AOUT0
VCOM
O
I
Channel 0 analog output pin
Common Voltage Pin, AVDD/2
Normally connected to AVSS with a 0.1uF ceramic capacitor in parallel
with a 10uF electrolytic cap.
Analog Power Supply Pin
20
AVDD
-
21
AVSS
-
Analog Ground pin
22
VREF
I
Voltage Reference Input Pin
The differential Voltage between this pin and AVSS set the analog output
range. Normally connected to AVSS with a 0.1uF ceramic capacitor.
Zero Input Detect Pin
23
DZF
O
24
TST1
I
Test Pin
Must be left floating or tied to AVSS.
Note: All input pins except pull-down pins should not be left floating.
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