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參數(shù)資料
| 型號(hào)： | AK4183VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | I2C Touch Screen Controller |
| 中文描述： | 觸摸屏控制器的I2C |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 173K |
| 代理商： | AK4183VT |
ASAHI KASEI
[AK4183]
[Data validity]
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
MS0500-E-00
2006/04
9
SCL
SDA
data line
stable;
data valid
change
of data
allowed
Figure 6 Bit Transfer on the I2C-Bus
[ACKNOWLEDGE]
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the SDA
line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that that
it remains stable “L” during “H” period of this clock pulse. The AK4183 will generates an acknowledge after each byte has been
received.
In the read mode, the slave, AK4183 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge.
If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data. If an
acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition.
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
1
9
8
START
CONDITION
not acknowledge
clock pulse for
acknowledgement
S
2
Figure 7 Acknowledge
[Address Byte]
The sequence of writing data is shown Figure 10. The address byte, which includes seven bits of slave address and one bit of R/W
bit, is sent after the START condition. If the transmitted slave address matches an address for one of the device, the receiver who
has been addressed pulls down the SDA line (acknowledge).
The most significant six bits of the slave address are fixed as “100100”. The next one bit is CAD0 (device address bit). This bit
identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets CAD0 bit. The eighth bit (LSB) of the address
byte (R/W bit) defines whether the master requests a write or read operation. A “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
1
0
0
1
0
0
CAD0
R/W
(CAD0 should match with CAD0 pins)
Figure 8 Address Byte
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4184 | TSC with Keypad Scanner and GPIO Expander |
| AK4184VG | TSC with Keypad Scanner and GPIO Expander |
| AK4220 | 7:3 Audio Switch and 6:3 Video Switch |
| AK4220VQ | 7:3 Audio Switch and 6:3 Video Switch |
| AK4250 | Output Coupling Capacitor-less Video Amp with LPF |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4184 | 制造商:AKM 制造商全稱:AKM 功能描述:Analog I/F IC which includes 4-wire resistive Touch Screen Controller |
| AK4184A | 制造商:AKM 制造商全稱:AKM 功能描述:TSC with Keypad Scanner and GPIO Expander |
| AK4184AEG | 制造商:AKM 制造商全稱:AKM 功能描述:TSC with Keypad Scanner and GPIO Expander |
| AK4184VG | 制造商:AKM 制造商全稱:AKM 功能描述:TSC with Keypad Scanner and GPIO Expander |
| AK4185 | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power Touch Screen Controller with SPI? Interface |
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