
[AK4145] 
DC CHARACTERISTICS 
(Ta=-20
~
 85
°
C; AVDD=TVDD=1.7~3.6V, DVDD=1.7~1.9V) 
Parameter 
High-Level Input Voltage  
TVDD < 2.7V 
TVDD 
≥
 2.7V 
Low-Level Input Voltage  
TVDD < 2.7V 
TVDD 
≥
 2.7V 
Low-Level Output Voltage (SDA pin: Iout= 3mA) 
Input Leakage Current 
Symbol
VIH 
VIH 
VIL 
VIL 
VOL 
Iin 
min 
typ 
- 
- 
- 
- 
- 
- 
Max 
- 
- 
Units
V 
V 
V 
V 
V 
μ
A 
80%TVDD 
70%TVDD 
- 
- 
- 
- 
20%TVDD 
30%TVDD 
0.4 
±
 10 
SWITCHING CHARACTERISTICS 
(Ta=-20
~
 85
°
C; AVDD=2.7 ~ 3.6V, TVDD=1.7~3.6V, DVDD=1. 7~1.9V) 
Parameter 
Master Clock Frequency
Duty Cycle  
LRCK Frequency
Duty Cycle 
Audio Interface Timing 
BICK Period 
BICK Pulse Width Low 
Pulse Width High 
BICK rising to LRCK Edge                           (
Note 6
) 
LRCK Edge to BICK rising                           (
Note 6
) 
SDTI Hold Time 
SDTI Setup Time 
Control Interface Timing (I
2
C Bus) 
SCL Clock Frequency 
Bus Free Time Between Transmissions 
Start Condition Hold Time  
(prior to first clock pulse) 
Clock Low Time 
Clock High Time 
Setup Time for Repeated Start Condition 
SDA Hold Time from SCL Falling                 (
Note 7
) 
SDA Setup Time from SCL Rising 
Rise Time of Both SDA and SCL Lines 
Fall Time of Both SDA and SCL Lines 
Setup Time for Stop Condition 
Pulse Width of Spike Noise Suppressed by Input Filter 
Capacitive load on bus 
Reset Timing 
PDN Pulse Width                                          (
Note 8
) 
Note 6. BICK rising edge must not occur at the same time as LRCK edge.  
Note 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 8. The AK4145 can be reset by bringing the PDN pin = “L”. 
Note 9. I
2
C is a registered trademark of Philips Semiconductors. 
Symbol 
fCLK 
dCLK 
fs 
Duty 
tBCK 
tBCKL 
tBCKH 
tBLR 
tLRB 
tSDH 
tSDS 
min 
8.192 
40 
32 
45 
1/128fs
30 
30 
20 
20 
20 
20 
- 
1.3 
0.6 
1.3 
0.6 
0.6 
0 
0.1 
- 
- 
0.6 
- 
0 
150 
typ 
max 
36.8640
60 
48 
55 
Units
MHz
% 
kHz 
% 
ns 
ns 
ns 
ns 
ns 
ns 
ns 
kHz 
μ
s 
μ
s 
μ
s 
μ
s 
μ
s 
μ
s 
μ
s 
μ
s 
μ
s 
μ
s 
ns 
pF 
ns 
fSCL 
tBUF 
tHD:STA 
tLOW 
tHIGH 
tSU:STA 
tHD:DAT 
tSU:DAT 
tR 
tF 
tSU:STO 
tSP 
Cb 
tPD 
400 
- 
- 
- 
- 
- 
- 
- 
0.3 
0.3 
- 
50 
400 
Rev. 0.3-PB 
2007/12 
- 6 -