參數(shù)資料
型號(hào)： AK4127
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 192kHz / 24Bit High Performance Asynchronous SRC
中文描述： 192kHz的/ 24位高性能異步鋼骨混凝土
文件頁(yè)數(shù)： 2/29頁(yè)
文件大小： 489K
代理商： AK4127
[AK4127]
TABLE OF CONTENTS
GENERAL DESCRIPTION...............................................................................................................................................1
FEATURES........................................................................................................................................................................1
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Ordering Guide ...........................................................................................................................................................3
Pin Layout .....................................................................................................................................................................3
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Compatibility with AK4125........................................................................................................................................4
PIN/FUNCTION ................................................................................................................................................................5
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Handling of Unused pins.............................................................................................................................................6
ABSOLUTE MAXIMUM RATINGS ...............................................................................................................................6
RECOMMENDED OPERATING CONDITIONS............................................................................................................6
SRC CHARACTERISTICS...............................................................................................................................................7
FILTER CHARACTERISTICS.........................................................................................................................................8
DC CHARACTERISTICS.................................................................................................................................................9
SWITCHING CHARACTERISTICS ................................................................................................................................9
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Timing Diagram........................................................................................................................................................11
OPERATION OVERVIEW.............................................................................................................................................13
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System Clock & Audio Interface Format for Input PORT........................................................................................13
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System Clock & Audio Interface Format for Output PORT.....................................................................................15
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Cascade TDM Mode.................................................................................................................................................18
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Soft Mute Operation..................................................................................................................................................19
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Dither ........................................................................................................................................................................20
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System Reset.............................................................................................................................................................20
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Internal Reset Function for Clock Change................................................................................................................21
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Sequence of Changing Clocks ..................................................................................................................................21
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UNLOCK pin............................................................................................................................................................21
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PLL Loop Filter.........................................................................................................................................................22
SYSTEM DESIGN...........................................................................................................................................................23
PACKAGE.......................................................................................................................................................................27
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Material & Lead finish..............................................................................................................................................27
MARKING.......................................................................................................................................................................28
REVISION HISTORY.....................................................................................................................................................28
IMPORTANT NOTICE...................................................................................................................................................29
MS0593-E-01
2007/07
- 2 -
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