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參數(shù)資料
| 型號： | AK4124VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192KHZ/ 24BIT HIGH PERFORMANCE ASYNCHRONOUS SRC |
| 中文描述： | 192kHz的/ 24位高性能異步鋼骨混凝土 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 220K |
| 代理商： | AK4124VF |
ASAHI KASEI
[AK4124]
MS0288-E-01
2004/08
- 13 -
ILRCK
IBICK(64fs)
0 1
2
24
31 0
1 2
1
0
31
24
8
9
8 9
SDTI(i)
Don't Care
0
8
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
23
8
Don't Care
23
1
Figure 5. Mode 4 Timing
System Clock & Audio Interface Format for Output PORT
The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 pins
select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when PDN pin = “L”.
The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of OBICK. Select the audio interface format when PDN
pin = “L”. When in BYPASS mode, both IBICK and OBICK are fixed to 64fs.
CMODE
2
1
0
L
L
L
Master
1
L
L
H
Master
2
L
H
L
Master
3
L
H
H
Master
4
H
L
L
Slave
5
H
L
H
Master
6
H
H
L
Master
7
H
H
H
Master (Bypass)
Table 3. Master/Slave Control (Output PORT)
Mode
ODIF1
ODIF0
0
L
L
1
L
H
2
H
L
3
H
H
Table 4. Output Audio Interface Format 1 (Output PORT)
Mode
CMODE
CMODE0
Master / Slave
OMCLK
fso
256fso
384fso
512fso
768fso
8k
～
108kHz
8k
～
108kHz
8k
～
54kHz
8k
～
54kHz
8k
～
216kHz
8k
～
216kHz
8k
～
216kHz
8k
～
216kHz
Not used. Set to DVSS.
128fso
192fso
Not used. Set to DVSS.
SDTO Format
LSB justified
(Reserved)
MSB justified
I
2
S Compatible
OBICK Frequency
MSB justified, I
2
S
≥
32fso
≥
36fso
≥
40fso
≥
48fso
Mode Master / Slave
OBIT1
OBIT0
SDTO
OLRCK
OBICK
LSB justified
0
1
2
3
4
5
6
7
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
16bit
18bit
20bit
24bit
16bit
18bit
20bit
24bit
Slave
CMODE2-0 =
“HLL”
Input
Input
64fso
Master
Except
CMODE2-0 =
“HLL”
Output
Output
64fso
Table 5. Output Audio Interface Format 2 (Output PORT)
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