參數(shù)資料
型號(hào): AK4121AVF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Asynchronous Sample Rate Converter
中文描述: 異步采樣率轉(zhuǎn)換器
文件頁(yè)數(shù): 16/19頁(yè)
文件大小: 353K
代理商: AK4121AVF
[AK4121A]
SYSTEM DESIGN
Figure 13 and Figure 14 illustrate typical system connection diagrams. The evaluation board [AKD4121A]
demonstrates this application circuit, the optimum layout, and power supply arrangement and performance
measurement results.
FILT
AVSS
PDN
SMUTE
DEM0
DEM1
ILRCK
IBICK
SDTI
IDIF0
IDIF1
IDIF2
VDD
DVSS
TVDD
MCLK
OLRCK
OBICK
SDTO
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
AK4121A
10u
+
0.1u
+3.3~5V
Digital (*1)
0.1u
DSP1
1.0n
DSP2
Control
Mode setting
(fix to “H” or “L”)
4.7u
560
fsi
fso
+3.3V Analog
Figure 13. Example of a typical design (Slave Mode)
FILT
AVSS
PDN
SMUTE
DEM0
DEM1
ILRCK
IBICK
SDTI
IDIF0
IDIF1
IDIF2
VDD
DVSS
TVDD
MCLK
OLRCK
OBICK
SDTO
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
AK4121A
10u
+
0.1u
+3.3~5V
Digital (*1)
0.1u
DSP1
1.0n
DSP2
Control
Mode setting
(fix to “H” or “L”)
4.7u
560
fsi
fso
+3.3V Analog
64fso
256fso
Figure 14. Example of a typical design (Master Mode; MCLK=256fso)
*1. TVDD should be the same as the maximum input voltage.
MS0337-E-02
2007/07
- 16 -
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