參數(shù)資料
型號(hào)： AK4110
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:37; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:14-37 RoHS Compliant: No
中文描述： 高功能96kHz的24位迪爾
文件頁(yè)數(shù)： 16/31頁(yè)
文件大?。?/td> 304K
代理商： AK4110
ASAHI KASEI
[AK4112A]
MS0020-E-00
2000/3
- 16 -
n
Error Handling
There are the following five factors which ERF pin goes “H”. ERF pin shows the status of the internal PLL operation and
it is “L” when the PLL is OFF (Clock Operation Mode 1).
1.
Unlock Error
2.
Parity Error
3.
Biphase Error
4.
Frame length Error
5.
STC (Status Change) flag=“1”
: “H” when the PLL goes UNLOCK state.
: Updated every sub-frame cycle.
: Updated every sub-frame cycle
: Updated every sub-frame cycle
: Holds “1” until reading 03H.
In Parallel Mode, ERF pin outputs the ORed signal including the factors of 1,2,3 and 4. Once ERF pin goes ”H”, it
maintains “H” for 1024/fs cycles after the all error factors are removed. Table 11 shows the state of each output pins
when the ERF pin is “H”. The Frame length Error is occurred when the interval of preamble in biphase signal is incorrect.
When unlock state, the channel status bits are not updated and the previous data is maintained.
Error
Unlock Error
Parity Error
Biphase Error
Frame Length Error
AUTO
“L”
Output
Output
Output
SDTO
“L”
V
“L”
Output
Output
Output
Previous Data
Previous Data
Previous Data
Table 11. Error handling (Parallel Mode)
In Serial Mode, ERF pin outputs the ORed signal including the factors of 1,2,3,4 and 5. However, Parity, Biphase and
Frame Length Error can be masked by MPAR bit, and the STC flag can be masked by MSTC bit. When those are masked
by each bit, the error factor does not affect ERF pin operation. The STC flag is set whenever a comparison between the
last sample of bits D5-0 of the receiver status 1 register (03H) and the new sample are different This comparison is made
every fs cycle. The STC flag is reset by reading the register 03H. This flag is also disabled during the first block after
reset.
Once ERF pin goes ”H”, it maintains “H” for 1024/fs cycles (can be changed by ERFH0-1 bits) after the all error factors
(In case of STC, from STC flag “1” to reading 03H) are removed. Once PAR, BIP, FRERR, V or UNLOCK bit goes “1”,
it returns “0” by reading Receiver Status 2 (04H). When unlock state, the channel status bits are not updated and the
previous data is maintained.
Register
BIP
Pin
Error
& Status
Unlock Error
Parity Error
Biphase Error
Frame Length Error
Status change
UNLOCK
1
0
0
0
0
PAR
0
1
0
0
0
FRERR
0
0
0
1
0
STC
0
0
0
0
1
AUTO
“L”
Output
Output
Output
Output
SDTO
“L”
V
TX
0
0
1
0
0
“L”
Output
Output
Output
Output
Output
Output
Output
Output
Output
Previous Data
Previous Data
Previous Data
Output
Table 12. Error handling (Serial Mode; MPAR=1, MSTC=1)
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