參數(shù)資料
型號： AK410A
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Quad Outputs 192kHz 24-Bit DIT
中文描述： 四輸出192kHz的24位動態(tài)網(wǎng)
文件頁數(shù)： 21/29頁
文件大小： 331K
代理商： AK410A
ASAHI KASEI
[AK4101A]
MS0250-E-00
2003/07
- 21 -
n
Serial Control Interface
In asynchronous mode, four of the dual function pins become CSN, CCLK, CDTI and CDTO, a 4 wire microprocessor
interface. The internal 66 byte control register can then be read and written. The contents of the control register define,
in part, the mode of operation for the AK4101A. Figure 19 illustrates the serial data flow associated with SCI read and
write operations. C1-0 bits are the chip address. The AK4101A looks for C1-0 bits to be a “11” before responding to the
incoming data. R/W is the Read/Write bit which is “0” for a read operation and “1” for a write operation. The register
address contained in A7-0 bits is decoded to select a particular byte of the control register. D7-0 bits on CDTI pin is the
control data coming from the microprocessor during a write operation. D7-0 bits on CDTO pin is the contents of the
addressed byte from the control register requested during a read operation. The address and data bits are framed by CSN
pin = “0”. During a write operation, each address and data bit is sampled on the rising edge of CCLK. During a read
operation, the address bits are sampled on the rising edge of CCLK while data on CDTO is output on the falling edge of
CCLK. CCLK has a maximum frequency of 5 MHz.
CSN
CDTI
CCLK
C1
0
1
2
3
4
5
6
7
16
17
18
19
20
21
22
23
D4
D5
D6
D7
*
*
*
*
*
C0
R/W
D0
D1
D2
D3
CDTO
Hi-Z (with pull-down resistor)
WRITE
CDTI
C1
D4
D5
D6
D7
*
*
*
*
*
C0
R/W
D0
D1
D2
D3
CDTO
Hi-Z (with pull-down resistor)
READ
D4
D5
D6
D7
D0
D1
D2
D3
Hi-Z
A7
8
9
10
11
12
13
14
15
A1
A2
A3
A4
A5
A6
A0
A7
A1
A2
A3
A4
A5
A6
A0
“L”
C1-C0: Chip Address (Fixed to “11”)
R/W:
READ/WRITE (0:READ, 1:WRITE)
*:
Don’t care
A7-A0: Register Address
D7-D0: Control Data
Figure 19. Control I/F Timing
AK4101A
CSN
CCLK
CDTI
CDTO
CSN
CCLK
CDTI
CDTO
AK4101A
μ
P
CSN1
CCLK
CDTI
CDTO
CSN2
Figure 20. Typical connection with
μ
P
Note: External pull-up resistor should not be attached to CDTO pins
since CDTO pin is internally connected to the pull-down resistor.
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