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參數(shù)資料
| 型號(hào)： | AK2307LV |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | SPEECH CODEC for Digital Key telephone (5.0V/3.3V) |
| 中文描述： | 語音編解碼器的數(shù)字按鍵電話（5.0V/3.3V） |
| 文件頁數(shù)： | 6/39頁 |
| 文件大?。?/td> | 468K |
| 代理商： | AK2307LV |
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ASAHI KASEI [AK2307/LV]
FUNCTIONAL
DISCRIPTIONS
1. SERIAL INTERFACE
The internal registers can be read/written via serial CPU interface which consists of SCLK, DATA, and CSN
pin.
1 word consists of 16bits. The first 3bits are the instruction code which specifies read or write.
The following 4bits specify the address. The rest of 8bits are the data stored in the internal registers.
Table1-A CPU I/F ADDRESS/DATA STRUCTURE
B15
B14
B13
B12
B11
B10
B9
B8
MS0190-E-05
2005/12
6
B7
B6
B5
B4
B3
B2
B1
B0
I2
I1
I0
A3
A2
A1
A0
*
D7
D6
D5
D4
D3
D2
D1
D0
Instruction code
(3 bit )
Address
(4bit)
*
Data for internal registers
(8bit)
*)Dummy bit for adjusting the I/O timing when reading register.
Table1-B INSTRUCTION CODE
I2
I1
I0
Read/Write
1
1
0
Read
1
1
1
Write
Others
No action
1-2 Timing of the Serial Interface
SCLK and DATA timing in WRITE/READ operation
(1) Input data are loaded into the internal shift register at the rising edge of SCLK.
(2) The rising edge of SCLK is counted after the falling edge of CSN.
(3) When CSN is “L” and more than 16 SCLK pulses:
[WRITE]
Data are loaded into the internal register at the rising edge of the SCLK 16
th
pulse.
[READ]
DATA pin becomes an input pin at the falling edge of the SCLK 16
th
pulse.
CSN timing and WRITE/READ CANCELLATION
(1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16
th
pulse.
(2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16
th
pulse.
SERIAL WRITE/READ ACCESS timing (SERIAL ACCESS MODE)
(1) Serial write and read operation will be done by feeding the another 16 SCLK pulse and
data after 1
write or read operation.
(2) It is not necessary to make CSN high between 1
st
operation and 2
nd
operation.
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